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1. general description the p89v660/662/664 are 80c51 microcontrollers with 16 kb/32 kb/64 kb flash and 512 b/1 kb/2 kb of data ram. these devices are designed to be drop-in and software compatible replacements for the p89c660/662/664 devices. both the in-system programming (isp) and in-application programming (iap) boot codes are upward compatible. additional features of the p89v660/662/664 devices when compared to the p89c660/662/664 devices are the inclusion of a secondary 100 khz byte-wide i 2 c-bus interface, an spi in terface, four addit ion i/o pins (port 4), and the ability to erase code memory in 128-byte pages. the iap capability combined wit h the 128-byte page size allows for efficient use of the code memory for non-volatile data storage. 2. features and benefits 2.1 principal features ? dual 100 khz byte-wide i 2 c-bus interfaces ? 128-byte page erase for efficient use of code memory as non-volatile data storage ? 0 mhz to 40 mhz operating frequency in 12x mode, 20 mhz in 6x mode ? 16 kb/32 kb/64 kb of on-chip flash user code memory with isp and iap ? 512 b/1 kb/2 kb ram ? spi (serial peripheral interface) and enhanced uart ? pca (programmable counter array) wi th pwm and capture/compare functions ? three 16-bit timers/counters ? four 8-bit i/o ports, one 4-bit i/o port ? watchdog timer (wdt) 2.2 additional features ? 30 ms page erase, 150 ms block erase ? support for 6-clock (default) or 12-clock mode selection via isp or parallel programmer ? plcc44 and tqfp44 packages ? ten interrupt sources with four priority levels ? second dptr register ? low emi mode (ale inhibit) ? power-down mode with external interrupt wake-up p89v660/662/664 8-bit 80c51 5 v low power 16 kb/32 kb/64 kb flash microcontroller with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi rev. 3.1 ? 17 october 2011 product data sheet
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 2 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi ? idle mode 2.3 comparison to th e p89c660/662/664 devices ? spi interface . the p89v660/662/664 devices include an spi interface that was not present on the p89c660/662/664 devices. ? dual i2c-bus interfaces . the p89v660/662/664 devices have two i 2 c-bus interfaces. the p89c660/662/66 4 devices have one. ? more i/o pins . the p89v660/662/664 devices have an additional four-bit i/o port, port 4. ? the 6x/12x mode on thep89v660/662/664 devices is programmable and erasable using isp and iap as well as parallel programmer mode. the p89c660/662/664 devices could only be switched using parallel programmer mode. ? smaller block sizes . the smallest block size on the p89c660/662/664 devices was 8 kb. the p89v660/662/664 devices have a page size of 128 b. these small pages can be erased and reprogrammed using iap function calls making use of the code memory for non-volatile data storage practical. each page erase is 30 ms or less. the iap and isp code in p89v660/662/664 devices support these 128-byte page operations. in addition, the iap and isp code uses multiple page erase operations to emulate the erasing of the larger block sizes (8 kb and 16 kb to maintain firmware compatibility). ? status bit versus status byte . the p89v660/662/664 devices used a status byte to control the automatic entry into isp mode following a reset. on the p89v660/662/664 devices this has changed to a single status bit. since the isp entry was based on the zero/non-zero value of the status byte this is an almost identical operation on the p89v660/662/664 devices. ? faster block erase . the erase time for the entire user code memory of the p89v660/662/664 devices is 150 ms. 3. ordering information table 1. ordering information type number package name description version p89v662fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 p89v662fbc tqfp44 plastic thin quad flat package; 44 leads; body 10 ? 10 ? 1.0 mm sot376-1 p89v664fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 p89v664fbc tqfp44 plastic thin quad flat package; 44 leads; body 10 ? 10 ? 1.0 mm sot376-1
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 3 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 3.1 ordering options 4. block diagram table 2. ordering options type number flash memory temperature range frequency p89v662fa 32 kb ? 40 ? cto+85? c 0 mhz to 40 mhz p89v662fbc 32 kb p89v664fa 64 kb p89v664fbc 64 kb fig 1. block diagram high performance 80c51 cpu 16 kb/32 kb/64 kb code flash 0.5 kb/1 kb/ 2 kb data ram port 2 port 1 port 0 oscillator internal bus crystal or resonator 002aab908 uart pca programmable counter array port 3 timer 2 timer 0 timer 1 spi xtal1 xtal2 primary i 2 c-bus watchdog timer secondary i 2 c-bus port 4 p4[7:0] p3[7:0] p2[7:0] p1[7:0] p0[7:0] txd rxd t0 spiclk mosi miso ss t1 t2 t2ex scl sda scl_1 sda_1 cex[4:0] p89v660/662/664
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 4 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 5. pinning information 5.1 pinning fig 2. plcc44 pin configuration p89v660/662/664 p1[5]/cex2 p0[4]/ad4 p1[6]/scl p0[5]/ad5 p1[7]/sda p0[6]/ad6 rst p0[7]/ad7 p3[0]/rxd p4[1]/sda_1/miso p3[1]/txd p2[7]/a15 p3[4]/t0/cex3 p2[6]/a14 p3[5]/t1/cex4 p2[5]/a13 p1[4]/cex1 p1[3]/cex0 xtal2 p1[2]/eci xtal1 p1[1]/t2ex v ss p1[0]/t2 p4[0]/scl_1/spiclk p4[2]/mosi p2[0]/a8 v dd p2[1]/a9 p0[0]/ad0 p2[2]/a10 p0[1]/ad1 p2[3]/a11 p0[2]/ad2 p2[4]/a12 p0[3]/ad3 002aab909 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ea ale/prog psen p3[6]/wr p3[7]/rd p3[3]/int1 p3[2]/int0 p4[3]/ss
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 5 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 3. tqfp44 pin configuration p89v660/662/664 p1[5]/cex2 p0[4]/ad4 p1[6]/scl p0[5]/ad5 p1[7]/sda p0[6]/ad6 rst p0[7]/ad7 p3[0]/rxd p4[1]/sda_1/miso p3[1]/txd p2[7]/a15 p3[4]/t0/cex3 p2[6]/a14 p3[5]/t1/cex4 p2[5]/a13 p1[4]/cex1 p1[3]/cex0 xtal2 p1[2]/eci xtal1 p1[1]/t2ex v ss p1[0]/t2 p4[0]/scl_1/spiclk p4[2]/mosi p2[0]/a8 v dd p2[1]/a9 p0[0]/ad0 p2[2]/a10 p0[1]/ad1 p2[3]/a11 p0[2]/ad2 p2[4]/a12 p0[3]/ad3 002aab910 ea ale/prog psen p3[6]/wr p3[7]/rd p3[3]/int1 p3[2]/int0 p4[3]/ss 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 6 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 5.2 pin description table 3. pin description symbol pin type description tqfp44 plcc44 p0[0] to p0[7] i/o port 0: port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have ?1?s written to them float, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when making the transition to ?1?s. external pull-ups are required as a general purpose i/o port. p0[0]/ad0 37 43 i/o p0[0] ? port 0 bit 0. i/o ad0 ? address/data bit 0. p0[1]/ad1 36 42 i/o p0[1] ? port 0 bit 1. i/o ad1 ? address/data bit 1. p0[2]/ad2 35 41 i/o p0[2] ? port 0 bit 2. i/o ad2 ? address/data bit 2. p0[3]/ad3 34 40 i/o p0[3] ? port 0 bit 3. i/o ad3 ? address/data bit 3. p0[4]/ad4 33 39 i/o p0[4] ? port 0 bit 4. i/o ad4 ? address/data bit 4. p0[5]/ad5 32 38 i/o p0[5] ? port 0 bit 5. i/o ad5 ? address/data bit 5. p0[6]/ad6 31 37 i/o p0[6] ? port 0 bit 6. i/o ad6 ? address/data bit 6. p0[7]/ad7 30 36 i/o p0[7] ? port 0 bit 7. i/o ad7 ? address/data bit 7. p1[0] to p1[7] [1] i/o with internal pull-up port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. the port 1 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 1 pins t hat are externally pulled low will source current (i il ) because of the internal pull-ups. p1[5], p1[6], p1[7] have high current drive of 16 ma. p1[0]/t2 40 2 i/o p1[0] ? port 1 bit 0. i t2 ? external count input to timer/counter 2 or clock-out from timer/counter 2 p1[1]/t2ex 41 3 i/o p1[1] ? port 1 bit 1. i t2ex : timer/counter 2 capture/re load trigger and direction control p1[2]/eci 42 4 i/o p1[2] ? port 1 bit 2. i eci ? external clock input. this signal is the external clock input for the pca. p1[3]/cex0 43 5 i/o p1[3] ? port 1 bit 3. i/o cex0 ? capture/compare external i/o for pca module 0. each capture/compare module connects to a port 1 pin for external i/o. when not used by the pca, this pin can handle standard i/o.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 7 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi p1[4]/cex1 44 6 i/o p1[4] ? port 1 bit 4. i/o cex1 ? capture/compare external i/o for pca module 1 p1[5]/cex2 1 7 i/o p1[5] ? port 1 bit 5. i/o cex2 ? capture/compare external i/o for pca module 2 p1[6]/scl 2 8 i/o p1[6] ? port 1 bit 6. i/o scl ? i 2 c-bus serial clock input/output p1[7]/sda 3 9 i/o p1[7] ? port 1 bit 7. i/o sda ? i 2 c-bus serial data input/output p2[0] to p2[7] [1] i/o with internal pull-up port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 2 pins t hat are externally pulled low will source current (i il ) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addr ess (movx@dptr). in this application, it uses strong in ternal pull-ups when making the transition to ?1?s. p2[0]/a8 18 24 i/o p2[0] ? port 2 bit 0. o a8 ? address bit 8. p2[1]/a9 19 25 i/o p2[1] ? port 2 bit 1. o a9 ? address bit 9. p2[2]/a10 20 26 i/o p2[2] ? port 2 bit 2. o a10 ? address bit 10. p2[3]/a11 21 27 i/o p2[3] ? port 2 bit 3. o a11 ? address bit 11. p2[4]/a12 22 28 i/o p2[4] ? port 2 bit 4. o a12 ? address bit 12. p2[5]/a13 23 29 i/o p2[5] ? port 2 bit 5. o a13 ? address bit 13. p2[6]/a14 24 30 i/o p2[6] ? port 2 bit 6. o a14 ? address bit 14. p2[7]/a15 25 31 i/o p2[7] ? port 2 bit 7. o a15 ? address bit 15. p3[0] to p3[7] [1] i/o with internal pull-up port 3 : port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 3 pins t hat are externally pulled low will source current (i il ) because of the internal pull-ups. p3[0]/rxd 5 11 i p3[0] ? port 3 bit 0. i rxd ? serial input port. p3[1]/txd 7 13 o p3[1] ? port 3 bit 1. o txd ? serial output port. table 3. pin description ?continued symbol pin type description tqfp44 plcc44
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 8 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi p3[2]/int0 81 4i p3[2] ? port 3 bit 2. i int0 ? external interrupt 0 input. p3[3]/int1 91 5i p3[3] ? port 3 bit 3. i int1 ? external interrupt 1 input p3[4]/t0/cex3 10 16 i/o p3[4] ? port 3 bit 4. i t0 ? external count input to timer/counter 0. i/o cex3 ? capture/compare external i/o for pca module 3. p3[5]/t1/cex4 11 17 i/o p3[5] ? port 3 bit 5. i t1 ? external count input to timer/counter 1 i/o cex4 ? capture/compare external i/o for pca module 4 p3[6]/wr 12 18 o p3[6] ? port 3 bit 6. o wr ? external data memory write strobe p3[7]/rd 13 19 o p3[7] ? port 3 bit 7. o rd ? external data memory read strobe. p4[0] to p4[3] [1] i/o with internal pull-up port 4 : port 4 is a 4-bit bidirectional i/o port with internal pull-ups. port 4 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 4 pins t hat are externally pulled low will source current (i il ) because of the internal pull-ups. p4[0]/scl_1/ spiclk 17 23 i/o p4[0] ? port 4 bit 0. i/o scl_1 ? second i 2 c-bus serial clock input/output i/o spiclk ? serial clock input/output for spi p4[1]/sda_1/ miso 28 34 i/o p4[1] ? port 4 bit 1. i/o sda_1 ? second i 2 c-bus serial data input/output i/o miso ? master input/slave output for spi p4[2]/mosi 39 1 i/o p4[2] ? port 4 bit 2. i/o mosi ? master output/slave input for spi p4[3]/ss 61 2i p4[3] ? port 4 bit 3. i ss ? slave select input for spi psen 26 32 i/o program store enable : psen is the read strobe for external program memory. when the device is executing from internal program memory, psen is inactive (high). when the device is executing code from external program memory, psen is activated twice eac h machine cycle, ex cept that two psen activations are skipped during each access to external data memory. rst 4 10 i reset : while the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. ea 29 35 i external access enable : ea must be connected to v ss in order to enable the device to fetch code from the external program memory. ea must be strapped to v dd for internal program execution. table 3. pin description ?continued symbol pin type description tqfp44 plcc44
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 9 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi [1] port 1, 2, 3, and 4 enter the bidirectional state (except the i 2 c pins) with a weak pull-up after reset. in this state, the pins can be used as inputs or outputs. see the 80c51 family hardware description for details of the port structure. a reset does not assert the strong pull-up for two clock cycles for t hese ports which normally occurs when the port transitions from a low to a high state. you must first write a zero, then a logic one to enable the strong pull-up for two clock cycles. [2] ale loading issue: when ale pin experienc es higher loading (>30 pf) during the rese t, the microcontroller may accidentally en ter into modes other than normal working mode. the solution is to add a pull-up resistor of 3 k ? to 50 k ? to v dd , e.g., for ale pin. [3] for 6-clock mode, ale is emitted at 1 3 of crystal frequency. ale/prog 27 33 i/o address latch enable: ale is the output signal for latching the low byte of the address during an access to external memory. this pin is also the programming pulse input (prog ) for flash programming. normally the ale [2] is emitted at a constant rate of 1 6 the crystal frequency [3] and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to ?1?, ale is disabled. xtal1 15 21 i crystal 1 : input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 14 20 o crystal 2: output from the inverting oscillator amplifier. v dd 38 44 i power supply v ss 16 22 i ground table 3. pin description ?continued symbol pin type description tqfp44 plcc44
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 10 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6. functional description 6.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not defined. ? accesses to any defined sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled ?-?, ?0? or ?1? can only be written and read as follows: ? ?-? unless otherwise specified, must be written with ?0?, but can return any value when read (even if it was wr itten with ?0?). it is a reserved bit and may be used in future derivatives. ? ?0? must be written with ?0?, and will return a ?0? when read. ? ?1? must be written with ?1?, and will return a ?1? when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 11 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 4. special function registers * indicates special function registers (sfrs) that are bit addressable. name description sfr addr. bit functions and addresses msb lsb bit addresse7e6e5e4e3e2e1e0 acc* accumulator e0h auxrauxiliary function register8eh------extramao auxr1 auxiliary function register 1 a2h - - - gf2 0 - dps bit addressf7f6f5f4f3f2f1f0 b* b register f0h ccap0h module 0 capture high fah ccap1h module 1 capture high fbh ccap2h module 2 capture high fch ccap3h module 3 capture high fdh ccap4h module 4 capture high feh ccap0l module 0 capture low eah ccap1l module 1 capture low ebh ccap2l module 2 capture low ech ccap3l module 3 capture low edh ccap4l module 4 capture low eeh ccapm0 module 0 mode c2h - ecom_0 capp_0 capn_0 mat_0 tog_0 pwm_0 eccf_0 ccapm1 module 1 mode c3h - ecom_1 capp_1 capn_1 mat_1 tog_1 pwm_1 eccf_1 ccapm2 module 2 mode c4h - ecom_2 capp_2 capn_2 mat_2 tog_2 pwm_2 eccf_2 ccapm3 module 3 mode c5h - ecom_3 capp_3 capn_3 mat_3 tog_3 pwm_3 eccf_3 ccapm4 module 4 mode c6h - ecom_4 capp_4 capn_4 mat_4 tog_4 pwm_4 eccf_4 bit address df de dd dc db da d9 d8 ccon* pca counter control c0h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ch pca counter high f9h cl pca counter low e9h cmod pca counter mode c1h cidl wdte - - - cps1 cps0 ecf dptr data pointer (2 b) dph data pointer high 83h dpl data pointer low 82h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 12 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ec es1 es0 et1 ex1 et0 ex0 bit addressefeeedecebeae9 e8 ien1*interrupt enable 1 e8h-----es3es2et2 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h pt2 ppc ps1 ps0 pt1 px1 pt0 px0 ip0h interrupt priority 0 high b7h p t2h ppch ps1h ps0h pt1h px1h pt0h px0h bit address ff fe fd fc fb fa f9 f8 ip1*interrupt priority 1 91h------ps3ps2 ip1hinterrupt priority 1 high 92h------ps3ps2 bit address8786858483828180 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 bit address9796959493929190 p1* port 1 90h sda scl cex2 cex1 cex0 eci t2ex t2 bit addressa7a6a5a4a3a2a1a0 p2* port 2 a0h a15 a14 a13 a12 a11 a10 a9 a8 bit addressb7b6b5b4b3b2b1b0 p3* port 3 b0h rd wr cex4/t1 cex3/t0 int1 int0 txd rxd p4 port 4 a1h - - - - ss mosi miso/ sda_1 spiclk/ scl_1 pcon power control register 87h smod1 smod0 - pof gf1 gf0 pd idl bit addressd7d6d5d4d3d2d1d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p rcap2h timer2 capture high cbh rcap2l timer2 capture low cah bit address 9f 9e 9d 9c 9b 9a 99 98 s0con* serial port control 9 8h sm0/fe_ sm1 sm2 ren tb8 rb8 ti ri s0buf serial port data buffer register 99h saddr serial port a ddress register a9h table 4. special function registers ?continued * indicates special function registers (sfrs) that are bit addressable. name description sfr addr. bit functions and addresses msb lsb
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 13 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi [1] unimplemented bits in sfrs (labeled ?-?) are ?x?s (unknown) at all times. unless otherwise specified, ?1?s should not be writ ten to these bits since they may be used for other purposes in future derivatives. the reset values shown for these bits are ? 0?s although they are unknown when read. saden serial port address enable b9h bit address 87 [1] 86 [1] 85 [1] 84 [1] 83 [1] 82 [1] 81 [1] 80 [1] spcr spi control register d5h spi e spen dord mstr cpol cpha spr1 spr0 spsr spi configuration register aah spif wcol - - - - - - spdat spi data 86h sp stack pointer 81h s1dat i 2 c-bus data register dah s1adr i 2 c-bus slave address register dbh s1adr.6 s1adr .5 s1adr.4 s1adr.3 s1adr. 2 s1adr.1 s1adr.0 s1gc s1sta i 2 c-bus status register d9h sc4 sc3 sc2 sc1 sc0 0 0 0 s1con* i 2 c-bus control register d8h cr2 ens1 sta sto si aa cr1 cr0 s2dat i 2 c-bus data register e2h s2adr i 2 c-bus slave address register e3h s2adr.6 s2adr .5 s2adr.4 s2adr.3 s2adr. 2 s2adr.1 s2adr.0 s2gc s2sta i 2 c-bus status register e1h sc24 sc23 sc22 sc21 sc20 0 0 0 s2con* i 2 c-bus control register f8h cr22 ens21 sta2 sto2 si2 aa2 cr21 cr20 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control register 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit address cf ce cd cc cb ca c9 c8 t2con* timer2 control register c8h tf2 exf2 rclk tclk exen2 tr2 c/t 2cp/rl2 t2mod timer2 mode control c9h - - ent2 - - - t2oe dcen th0 timer 0 high 8ch th1 timer 1 high 8dh th2 timer 2 high cdh tl0 timer 0 low 8ah tl1 timer 1 low 8bh tl2 timer 2 low cch tmod timer 0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 wdtrst watchdog timer reset a6h table 4. special function registers ?continued * indicates special function registers (sfrs) that are bit addressable. name description sfr addr. bit functions and addresses msb lsb
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 14 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.2 memory organization the various p89v660/662/664 memory spaces are as follows: ? data 128 b of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? idata indirect data. 256 b of internal data memo ry space (00h:ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 b immediately above it. ? sfr special function registers. selected cpu re gisters and peripheral control and status registers, accessible only via direct addressing. ? xdata ?external? data or au xiliary ram. duplicates the classic 80c51 64 kb memory space addressed via the movx instruction using the dptr, r0, or r1. the p89v660/662/664 have 256/768/1792 b of on-chip xdata memory. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89v660/662/664 hav e 16/32/64 kb of on-chip code memory. 6.2.1 expanded data ram addressing the p89v660/662/664 have 512 b/1 kb/2 kb of ram. see figure 4 . to access the expanded ram, the extram bit must be set and movx instructions must be used. the extra memory is physically loca ted on the chip and logically occupies the first bytes of external memory ( addresses 000h to 0ffh/2ffh/6ffh). when extram = 1, the expanded ram is in directly addressed using the movx instruction in combination with any of the regi sters r0, r1 of the selected bank or dptr. accessing the expanded ram does not affect ports p0, p3[6] (wr ), p3[7] (rd ), or p2. with extram = 1, the expanded ram can be accessed as in the following example. expanded ram access (indirect addressing only): movx@dptr, a; dptr contains 0a0h the dptr points to location 0a0h and the data in the accumu lator is written to address 0a0h of the expanded ram rather than off- chip external memory. access to extram addresses that are not present on the device (above 0ffh for the 89v660, above 2ffh table 5. auxr - auxiliary register (address 8eh) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol ------extramao
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 15 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi for the 89v662, above 6ffh for the 89v664) will access external off-chip memory and will perform in the same way as the standard 8051, with p0 and p2 as data/address bus, and p3[6] and p3[7] as write and read timing signals. when extram = 0, movx @ri and movx @dptr will be similar to the standar d 8051. using movx @ri provides an 8-bit address wit h multiplexed data on port 0. other output port pins can be used to output higher orde r address bits. this provides external paging capabilities. using movx @dpt r generates a 16-bit address. this allows external addressing up the 64 kb. port 2 provides the high-order eight address bits (dph), and port 0 multiplexes the low order eight address bits (dpl) with data. both movx @ri and movx @dptr generates the necessary read and write signals (p3[6] - wr and p3[7] - rd ) for external memory use. ta b l e 7 shows external data memory rd , wr operation with extram bit. the stack pointer (sp) can be located anywhere within the 256 b of internal ram (lower 128 b and upper 128 b). the stack pointer may not be located in any part of the expanded ram. table 6. auxr - auxiliary register (address 8eh) bit description bit symbol description 7 to 2 - reserved for future use. should be set to ?0? by user programs. 1 extram internal/external ram access using movx @ri/@dptr. when ?1?, accesses internal xram with address specified in movx instruction. if address supplied with this instruction exceeds on-chip available xram, off-chip ram is accessed. wh en ?0?, every movx instructions targets external data memory by default. 0 ao ale off: disables/enables ale. ao = 0 results in ale emitted at a constant rate of 1 2 the oscillator frequency. in case of ao = 1, ale is active only during a movx or movc. table 7. external data memory rd , wr with extram bit auxr movx @dptr, a or movx a, @dptr movx @ri, a or movx a, @ri addr < 0100h (89v660) addr ? 0100h (89v660) addr = any addr < 0300h (89v662) addr ? 0300h (89v662) addr < 0700h (89v664) addr ? 0700h (89v664) extram = 0 rd /wr asserted rd /wr asserted rd /wr asserted extram = 1 rd /wr not asserted rd /wr asserted rd /wr not asserted
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 16 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.2.2 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps = 0, dptr0 is selected; when dps = 1, dptr1 is selected . quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1 (see figure 5 ). fig 4. internal and external data memory structure 000h 2ffh 00h ffh upper 128 b internal ram lower 128 b internal ram (indirect and direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh 000h external data memory external data memory 2ffh 0000h extram = 0 extram = 1 expanded ram 0300h (indirect addressing) (indirect addressing) (indirect addressing) ffffh 80h 7fh 002aaa517 expanded ram 768 b
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 17 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.2.3 reset at initial power-up, the port pins will be in a random st ate until the oscillator has started and the internal reset algorithm has weakly pu lled all pins high. powering up the device without a valid reset could cause the mcu to start executing instructions from an indeterminate location. such undefined states may inadvertently co rrupt the code in the flash. a system reset will not affect the on-chi p ram while the device is running, however, the contents of the on-chip ram during power-up are indeterminate. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start-up (usually several milliseconds for a low fr equency crystal), in addition to two machine cycles for a valid power-on reset. an example of a method to extend the rst signal is to implement a rc circui t by connecting the rst pin to v dd through a 10 f capacitor and to v ss through an 8.2 k ? resistor as shown in figure 6 . during initial power the pof flag in the pcon register is se t to indicate an initial power-up condition. the pof flag will remain active until cleared by software. following a reset condition, und er normal conditions, the mcu will start executing code from address 0000h in the user?s co de memory. however if either the psen pin was low when reset was exited, or th e status bit was set = 1, th e mcu will start executing code from the boot address. the boot address is formed using the value of the boot vector as the high byte of the address and 00h as the low byte. fig 5. dual data pointer organization table 8. auxr1 - auxiliary register 1 (address a2h) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol ----gf20-dps table 9. auxr1 - auxiliary register 1 (address a2h) bit description bit symbol description 7 to 4 - reserved for future use. should be set to ?0? by user programs. 3 gf2 general purpose user-defined flag. 2 0 this bit contains a hard-wired ?0?. allows toggling of the dps bit by incrementing auxr1, without interferin g with other bits in the register. 1 - reserved for future use. should be set to ?0? by user programs. 0 dps data pointer select. chooses one of two data pointers for use by the program. see text for details. dpl 82h dps = 0 dptr0 dps = 1 dptr1 external data memory dps 002aaa518 dph 83h dptr0 dptr1 auxr1 / bit0
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 18 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.3 flash memory 6.3.1 flash organization the p89v660/662/664 program memory consis ts of a 16/32/64 kb block for user code. the flash can be read or written in bytes and can be erased in 128 pages. a chip erase function will erase the entire user code memory and its associ ated security bits. there are three methods of erasing or programming the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-state routines through a common iap entry point. second, the on-chip isp bootloader may be invoked. this isp bootloader will, in turn, call low-st ate routines th rough the same common entry point that can be used by the end -user application. third, the flash may be programmed or erased using the parallel method by using a commercially available eprom programmer which supports this device. 6.3.2 features ? flash internal program memory with 128-byte page erase. ? internal boot block, containing low-stat e iap routines available to user code. ? boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. ? default loader providing isp via the serial port, located in upper end of program memory. ? programming and erase over the full operating voltage range. ? read/programming/erase using isp/iap. ? programming with industry-standard commercial programmers. ? 10000 typical erase/program cycles for each byte. ? 100 year minimum data retention. fig 6. power-on reset circuit 002aaa543 v dd v dd 8.2 k rst xtal2 xtal1 c 1 c 2 10 f
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 19 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.3.3 boot block when the microcontroller programs its own flash memory, all of the low level details are handled by code (bootloader) that is contained in a boot block. a user program calls the common entry point in the boot block with appropriate parameters to accomplish the desired operation. boot block operations include erase user code, program user code, program security bits, chip erase, etc. th e boot block logically overlays the program memory space from fc00h to ffffh, when it is enabled. the boot block may be disabled on-the-fly so that the upper 1 kb of user code is available to the user?s program. 6.3.4 power-on reset code execution the p89v660/662/664 contains two special flash elements: the boot vector and the boot status bit. following reset, the p89v660/662/ 664 examines the contents of the boot status bit. if the boot status bit is set to ze ro, power-up execution starts at location 0000h, which is the normal start address of the user?s application c ode. when the boot status bit is set to a value other than zero , the contents of the boot vect or are used as the high byte of the execution address and the low byte is set to 00h ta b l e 1 0 shows the factory default boot vector sett ing for this device. a factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated boot loader entry point to perform isp functions. 6.3.5 hardware activation of the bootloader the bootloader can also be executed by forcing the device into isp mode during a power-on sequence. this has the same effect as having a non-zero status byte. this allows an application to be built that will norma lly execute user code but can be manually forced into isp operation. if the factory default setting fo r the boot vector (fch) is changed, it will no longer poi nt to the factory pre-program med isp bootloade r code. after programming the flash, the status byte should be programmed to zero in order to allow execution of the user?s application code beginning at address 0000h. 6.3.6 isp isp is performed without remo ving the microcontroller from the system. the isp facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the p89v66 0/662/664 thro ugh the serial port. this firmware is provided by nxp and embedd ed within each p89v660/662/664 device. the nxp isp facility has made in-c ircuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins (v dd , v ss , txd, rxd, and rst). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 6.3.7 using isp the isp feature allows for a wide range of baud rates to be used in your application, independent of th e oscillator frequency. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts table 10. default boot vector values and isp entry points device default boot vector default bootloader entry point default bootloader code range p89v660/662/664 fch fc00h fc00h to ffffh
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 20 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi based on the oscillator frequency. the isp fe ature requires that an initial character (an uppercase u) be sent to the p89v660/662 /664 to establish the baud rate. the isp firmware provides auto-echo of received ch aracters. once baud ra te initialization has been performed, the isp firmware will only accept inte l hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc in the intel hex record, the ?nn? represents the number of data bytes in the record. the p89v660/662/664 will acce pt up to 32 data bytes. the ?aaaa? string represents the address of the first byte in the record. if ther e are zero bytes in the record, this field is often set to 0000. the ?rr? string indicates the re cord type. a record type of ?00? is a data record. a record type of ?01? indicates the end- of-file mark. in this application, additional record types will be added to indicate either commands or data for the isp facility. the maximum number of data bytes in a record is limited to 32 (decimal). isp commands are summarized in table 11 . as a record is received by the p89v660/662/664, the information in the record is stored internally and a checksum calculation is performed. the operation indicated by the record type is not performed until the entire record has been received. should an error oc cur in the checksum, the p8 9v660/662/664 will send an ?x? out the serial port indicating a checksum erro r. if the checksum calculation is found to match the checksum in the record, then th e command will be executed. in most cases, successful reception of the reco rd will be indicated by transmit ting a ?.? character out the serial port. table 11. isp hex record formats record type command/data function 00 program user code memory :nnaaaa00dd..ddcc where: nn = number of bytes to program aaaa = address dd..dd = data bytes cc = checksum example: :09000000010203040506070809ca 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field but value is a ?don?t care? cc = checksum example: :00000001ff 02 not used
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 21 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes in the record xxxx = required field but val ue is a ?don?t care? ff = subfunction code ss = selection code dd = data (if needed) cc = checksum subfunction code = 01 (erase blocks) ff = 01 ss = block code, as shown below block 0, 0k to 8k, 00h block 1, 8k to 16k, 20h block 0, 16k to 32k, 40h block 0, 32k to 48k, 80h block 0, 48k to 64k, c0h subfunction code = 04 (erase boot vector and status bit) ff = 04 ss = don?t care subfunction code = 05 (program security bits) ff = 05 ss = 00 program security bit 1 ss = 01 program security bit 2 ss = 02 program security bit 3 subfunction code = 06 (program stat us bit, boot vector, 6x/12x bit) ff = 06 dd = data (for boot vector) ss = 00 program status bit ss = 01 program boot vector ss = 02 program 6x/12x bit subfunction code = 07 (chip erase) erases code memory and security bits, programs default boot vector and status bit ff = 07 subfunction code = 08 (erase page, 128 b) ff = 08 ss = high byte of page address (a[15:8]) dd = low byte of page address (a[7:0]) example: :0300000308e000f2 (erase page at e000h) table 11. isp hex record formats ?continued record type command/data function
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 22 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 04 display device data or blank check :05xxxx04sssseeeeffcc where 05 = number of bytes in the record xxxx = required field but val ue is a ?don?t care? 04 = function code for display or blank check ssss = starting address, msb first eeee = ending address, msb first ff = subfunction 00 = display data 01 = blank check cc = checksum subfunction codes: example: :0500000400001fff00d9 (display from 0000h to 1fffh) 05 miscellaneous read functions :02xxxx05ffsscc where: 02 = number of bytes in the record xxxx = required field but val ue is a ?don?t care? 05 = function code for misc read ffss = subfunction and selection code 0000 = read manufacturer id 0001 = read device id 1 0002 = read device id 2 0003 = read 6x/12x bit (bit 7 = 1 is 6x, bit 7 = 0 is 12x) 0080 = read boot code version 0700 = read security bits 0701 = read status bit 0702 = read boot vector cc = checksum example: :020000050000f9 (display manufacturer id) 06 direct load of baud rate :02xxxx06hhllcc where: 02 = number of bytes in the record xxxx = required field but val ue is a ?don?t care? hh = high byte of timer t2 ll = low byte of timer t2 cc = checksum example: :02000006ffffcc (load t2 = ffff) table 11. isp hex record formats ?continued record type command/data function
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 23 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.3.8 iap method several iap calls are available for use by an application program to permit selective erasing, reading and programming of flash pages, security bits, security bits, status bit, and device id. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontroller?s registers before making a call to pgm_mtp at fff0 h. the iap calls are shown in ta b l e 1 2 . table 12. iap function calls iap function iap call parameters read id input parameters: r1 = 00h or 80h (wdt feed) dph = 00h dpl = 00h = manufacturer id dpl = 01h = device id 1 dpl = 02h = device id 2 dpl = 03h = 6x/12x bit (bit 7 = 1 = 6x) dpl = 80h = isp version number return parameter(s): acc = requested parameter erase 8 kb/16 kb code block input parameters: r1 = 01h or 81h (wdt feed) dpl=00h, block 0, 0kb to 8kb dpl = 20h, block 1, 8 kb to 16 kb dpl = 40h, block 2, 16 kb to 32 kb dpl = 80h, block 3, 32 kb to 48 kb dpl = c0h, block 4, 48 kb to 64 kb return parameter(s): acc = 00 = pass acc = !00 = fail program user code input parameters: r1 = 02h or 82h (wdt feed) dph = memory address msb dpl = memory address lsb acc = byte to program return parameter(s): acc = 00 = pass acc = !00 = fail read user code input parameters: r1 = 03h or 83h (wdt feed) dph = memory address msb dpl = memory address lsb return parameter(s): acc = device data
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 24 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.4 i 2 c-bus interface the i 2 c-bus uses two wires, serial clock (scl) and serial data (sda) to transfer information between devices connected to the bus, and has the following features: ? bidirectional data transfer between masters and slaves erase status bit and boot vector input parameters: r1 = 04h or 84h (wdt feed) dpl = don?t care dph = don?t care return parameter(s): acc = 00 = pass acc = !00 = fail program security bits input parameters: r1 = 05h or 85h (wdt feed) dpl = 00h = security bit 1 dpl = 01h = security bit 2 dpl = 02h = security bit 3 return parameter(s): acc = 00 = pass acc = !00 = fail program status bit, boot vector, 6x/12x bit input parameters: r1 = 06h or 86h (wdt feed) dpl = 00h = program status bit dpl = 01h = program boot vector dpl = 02h = 6x/12x bit acc = boot vector value to program return parameter(s): acc = 00 = pass acc = !00 = fail read security bits, status bit, boot vector input parameters: acc = 07h or 87h (wdt feed) dpl = 00h = security bits dpl = 01h = status bit dpl = 02h = boot vector return parameter(s): acc = 00 softice s/n-match 0 sb 0 dbl_clk erase page input parameters: r1 = 08h or 88h (wdt feed) dph = page address high byte dpl = page address low byte return parameter(s): acc = 00 = pass acc = !00 = fail table 12. iap function calls ?continued iap function iap call parameters
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 25 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi ? multimaster bus (n o central master) ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes a typical i 2 c-bus configuration is shown in figure 7 . depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c-bus: ? data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. ? data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by th e slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and st op conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c-bus will not be released. the p89v660/662/664 device provides two byte-oriented i 2 c-bus interfaces. for simplicity, the description in this text is written for the primary interface. however, unless otherwise noted, the description applies to the secondary i 2 c-bus interface with consideration given to the sfr?s addresses for the secondary interface. please note that the secondary i 2 c-bus interface uses quasi-bidirectio nal i/o pins instead of open-drain pins. the interface has four operation modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode the p89v660/662/664 cpu interfaces with the i 2 c-bus through four special function registers (sfrs): s1con (primary i 2 c-bus control register), s1dat (primary i 2 c-bus data register), s1sta (primary i 2 c-bus status register), and the s1adr (primary i 2 c-bus slave address register). fig 7. i 2 c-bus configuration other device with i 2 c-bus interface sda scl r pu r pu other device with i 2 c-bus interface p1[7]/sda p1[6]/scl p89v660/662/664 i 2 c-bus 002aab911
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 26 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.4.1 i 2 c-bus data register s1dat register contains the data to be transmitted or the data received. the cpu can read and write to this 8-bit register while it is not in the process of shifting a byte. thus this register should only be accessed when the si bit is set. data in s1dat remains stable as long as the si bit is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and after a byte has been received, the first bit of received data is located at the msb of s1dat. 6.4.2 i 2 c-bus slave address register the s1adr register is readable and writable, and is only used when the i 2 c-bus interface is set to slave mode. in master mode, this register has no effect. the lsb of s1adr is general call bit. when this bit is set, the general call address (00h) is recognized. 6.4.3 i 2 c-bus control register the cpu can read and write this register. there are two bits are affected by hardware: the si bit and the sto bit. the si bit is set by hardware and the sto bit is cleared by hardware. cr2:0 determines the scl source and frequency when the i 2 c-bus is in master mode. in slave mode these bits are ignored and the bus will automatically synchronize with any clock frequency up to 100 khz from the master i 2 c-bus device. timer 1 should be programmed by the user in 8 bit auto-reload mode (mode 2) when used as the scl source. see table 17 . the sta bit is start flag. setting this bit causes the i 2 c-bus interface to enter master mode and attempt transmitting a start condition or transmitting a repeated start condition when it is al ready in master mode. the sto bit is stop flag. setting this bit causes the i 2 c-bus interface to transmit a stop condition in master mode, or recovering from an error condition in slave mode. if the sta and sto are both set, then a stop condition is transmitted to the i 2 c-bus if it is in master mode, and transmits a start condition afterwards. if it is in slave mode, an internal stop condition will be generated , but it is not transmitted to the bus. table 13. i 2 c-bus slave address register (s 1adr - address dbh) bit allocation bit 7 6 5 4 3 2 1 0 symbol s1adr.6 s1adr.5 s1adr.4 s 1adr.3 s1adr.2 s1adr.1 s1adr.0 s1gc reset00000000 table 14. i 2 c-bus slave address register (s1 adr - address dbh) bit description bit symbol description 7:1 s1adr7:1 7 bit own slave address. when in mast er mode, the contents of this register has no effect. 0 s1gc general call bit. when set, the gen eral call address (00h) is recognized, otherwise it is ignored.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 27 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 15. i 2 c-bus control register (s1con - address d8h) bit allocation bit 7 6 5 4 3 2 1 0 symbol cr2 ens1 sta sto si aa cr1 cr0 resetx00000x0 table 16. i 2 c-bus control register (s1con - address d8h) bit description bit symbol description 7,1,0 cr2:0 scl clo ck selection. see ta b l e 1 7 . 2 aa the assert acknowledge flag. when set to 1, an acknowledge (low-state to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 1. the ?own slave address? has been received. 2. the general call address has been received while the general call bit (gc) in s1adr is set. 3. a data byte has been received while the i 2 c-bus interface is in the master receiver mode. 4. a data byte has been received while the i 2 c-bus interface is in the addressed slave receiver mode. when cleared to 0, an not acknowledge (high-state to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 1. a data byte has been received while the i 2 c-bus interface is in the master receiver mode. 2. a data byte has been received while the i 2 c-bus interface is in the addressed slave receiver mode. 3si i 2 c-bus interrupt flag. this bit is set when one of the 25 possible i 2 c-bus states is entered. when ea bit and ei2c (ien1.0) bit are both set, an interrupt is requested when si is set. must be cleared by software by writing 0 to this bit. 4 sto stop flag. sto = 1: in master mode, a stop condition is transmitted to the i 2 c-bus. when the bus detects the stop conditi on, it will clear sto bit automatically. in slave mode, setting this bit can recover from an error condition. in this case, no stop condition is transmitted to the bus. the hardware behaves as if a stop condition has been re ceived and it switches to ?not addressed? slave receiver mode. the sto flag is cleared by hardware automatically. 5 sta start flag. sta = 1: i 2 c-bus enters master mode, checks the bus and generates a start condition if the bus is free. if the bus is not free, it waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal clock generator. when the i 2 c-bus interface is already in master mode and some data is transmitted or received, it transmits a repeated start condition. sta may be set at any time, it may also be set when the i 2 c-bus interface is in an addressed slave mode. sta = 0: no start condition or repeated start condition will be generated. 6ens1i 2 c-bus interface enable. when set, enables the i 2 c-bus interface. when clear, the i 2 c-bus function is disabled. table 17. i 2 c-bus clock rates cr2:0 bit frequency at f osc 6-clock mode 12-clock mode f osc divided by 6 mhz 12 mhz 6 mhz 12 mhz 6x 12x 00047942347128256 001 54 107 27 54 112 224 010 63 125 31 63 96 192 011 75 150 37 75 80 160 100 12.5 25 6.25 12.5 480 960
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 28 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.4.4 i 2 c-bus status register this is a read-only register. it contains the status code of the i 2 c-bus interface. the least three bits are always 0. there are 26 possible status codes. when the code is f8h, there is no relevant information available and si bit is not set. all other 25 status codes correspond to defined i 2 c-bus states. when any of these states entered, the si bit will be set. refer to ta b l e 2 2 to ta b l e 2 5 for details. 6.4.5 i 2 c-bus operation modes 6.4.5.1 master transmitter mode in this mode data is transmitted from master to slave. before the master transmitter mode can be entered, s1con must be initialized as follows: cr2:0 define the bit rate (see ta b l e 1 7 ). ens1 must be set to 1 to enable the i 2 c-bus function. if the aa bit is 0, it will not acknowl edge its own slave addre ss or the general call address in the event of another device becoming master of the bus and it can not enter slave mode. sta, sto, and si bits must be cleared to 0. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case, the data direction bit (r/w) will be logic 0 indicating a write. data is transmitted 8 bits at a time. af ter each byte is transmitted, an acknowledge bit is received. start and stop conditions ar e output to indicate the beginning and the end of a serial transfer. 101 100 200 50 100 60 120 110 200 400 100 200 30 60 111 0.49 < 62.5 0.98 < 50.0 0.24 < 62.5 0.49 < 62.5 48 x (timer 1 reload) 96 x (timer 1 reload) table 17. i 2 c-bus clock rates ?continued cr2:0 bit frequency at f osc 6-clock mode 12-clock mode f osc divided by 6 mhz 12 mhz 6 mhz 12 mhz 6x 12x table 18. i 2 c-bus status register (s1sta - address d9h) bit allocation bit 7 6 5 4 3 2 1 0 symbol sc.4 sc.3 sc.2 sc.1 sc.0 0 0 0 reset00000000 table 19. i 2 c-bus status register (s1sta - address d9h) bit description bit symbol description 7:3 sc[4:0] i 2 c-bus status code. 2:0 - reserved, are always set to 0. table 20. i 2 c-bus control register (s1con - address d8h) bit 7 6 5 4 3 2 1 0 symbol cr2 ens1 sta sto si aa cr1 cr0 value bit rate 1 0 0 0 x bit rate bit rate
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 29 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi the i 2 c-bus will enter master transmitter mo de by setting the sta bit. the i 2 c-bus logic will send the start condition as soon as the bus is free. af ter the start condition is transmitted, the si bit is set, and the status code in s1sta should be 08h. this status code must be used to vector to an interrupt service routine where the user should load the slave address to s1dat and data direction bit (sla+w). the si bit must be cleared before the data transfer can continue. when the slave address and r/w bit have been transmitted and an acknowledgment bit has been received, the si bit is set again, and the possible status codes are 18h, 20h, or 38h for the master mode or 68h, 78h, or 0b 0h if the slave mode was enabled (setting aa = logic 1). the appropriate action to be ta ken for each of these status codes is shown in ta b l e 2 2 . 6.4.5.2 master receiver mode in the master receiver mode, data is rece ived from a slave transmitter. the transfer started in the same manner as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to i 2 c-bus data register (s1dat). the si bit must be cleared before the data transfer can continue. when the slave address and data dire ction bit have been transmitted and an acknowledge bit has been received, the si bit is set, and the status register will show the status code. for master mode, the possible stat us codes are 40h, 48h, or 38h. for slave mode, the possible status codes are 68h, 78h, or b0h. refer to ta b l e 2 4 for details. after a repeated start condition, i 2 c-bus may switch to the master transmitter mode. fig 8. format in the master transmitter mode s r/w a data data data transferred (n bytes + acknowledge) a a/a p slave address logic 0 = write logic 1 = read from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition 002aaa929 fig 9. format of master receiver mode s r a slave address logic 0 = write logic 1 = read from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition 002aaa930 data data data transferred (n bytes + acknowledge) a a p
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 30 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.4.5.3 slave receiver mode in the slave receiver mode, data bytes ar e received from a master transmitter. to initialize the slave receiver mode, the user should write the slave address to the slave address register (s1adr) and the i 2 c-bus control register (s1con) should be configured as follows: cr2:0 are not used for slave mode. ens1 must be set = 1 to enable i 2 c-bus function. aa bit must be set = 1 to acknowledge its own slave address or the general call address. sta, sto and si are cleared to 0. after s1adr and s1con are initia lized, the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0(w). if the direction bit is 1(r), it will enter slav e transmitter mode. after the address and the direction bit have been received, the si bit is set and a va lid status code can be read from the status register(s1sta). refer to ta b l e 2 5 for the status codes and actions. 6.4.5.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the tran sfer direction is reversed. serial data is transmitted via p1[7]/sda while the serial cl ock is input through p1[6]/scl. start and fig 10. a master receiver switches to master transmitter after sending repeated start s r a sla logic 0 = write logic 1 = read from master to slave from slave to master 002aaa931 data data data transferred (n bytes + acknowledge) a w a sla data a p a rs a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition sla = slave address rs = repeat start condition table 21. i 2 c-bus control register (s1con - address d8h) bit 7 6 5 4 3 2 1 0 symbol cr2 ens1 sta sto si aa cr1 cr0 value- 10001- - fig 11. format of slave receiver mode s w a slave address logic 0 = write logic 1 = read from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition rs = repeated start condition 002aaa932 data data data transferred (n bytes + acknowledge) a a/a p/rs
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 31 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi stop conditions are recognized as the beginning and end of a serial transfer. in a given application, the i 2 c-bus may operate as a master and as a slave. in the slave mode, the i 2 c-bus hardware looks for its own slave addres s and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontrollers wishes to become the bus master, the hardware wait s until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, the i 2 c-bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer. fig 12. format of slave transmitter mode s r a slave address logic 0 = write logic 1 = read from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition 002aaa933 data data data transferred (n bytes + acknowledge) a a p
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 32 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 13. i 2 c-bus serial interface block diagram internal bus 002aab912 address register comparator shift register 8 i2adr ack bit counter/ arbitration and sync logic 8 i2dat timing and control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1[7] p1[7]/sda p1[6]/scl p1[6] timer 1 overflow control registers and scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 33 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 22. master transmitter mode status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa 08h a start condition has been transmitted. load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received. 10h a repeat start condition has been transmitted. load sla+w or load sla+r x 0 0 x as above; sla+w will be transmitted; i 2 c-bus switches to master receiver mode. 18h sla+w has been transmitted; ack has been received. load data byte or000xdata byte will be transmitted; ack bit will be received. no s1dat action or 100xrepeated start will be transmitted. no s1dat action or 010xstop condition w ill be transmitted; sto flag will be reset. no s1dat action 110xstop condition followed by a start condition will be transmitted; sto flag will be reset. 20h sla+w has been transmitted; not-ack has been received. load data byte or000xdata byte will be transmitted; ack bit will be received. no s1dat action or 100xrepeated start will be transmitted. no s1dat action or 010xstop condition w ill be transmitted; sto flag will be reset. no s1dat action 110xstop condition followed by a start condition will be transmitted; sto flag will be reset. 28h data byte in s1dat has been transmitted; ack has been received. load data byte or000xdata byte will be transmitted; ack bit will be received. no s1dat action or 100xrepeated start will be transmitted. no s1dat action or 010xstop condition w ill be transmitted; sto flag will be reset. no s1dat action 110xstop condition followed by a start condition will be transmitted; sto flag will be reset.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 34 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 30h data byte in s1dat has been transmitted, not ack has been received. load data byte or000xdata byte will be transmitted; ack bit will be received. no s1dat action or 100xrepeated start will be transmitted. no s1dat action or 010xstop condition w ill be transmitted; sto flag will be reset. no s1dat action110xstop condition followed by a start condition will be transmitted. sto flag will be reset. 38h arbitration lost in sla+r/w or data bytes. no s1dat action or 000xi 2 c-bus will be released; not addressed slave will be entered. no s1dat action 100xa start condition will be transmitted when the bus becomes free. table 22. master transmitter mode ?continued status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa table 23. master receiver mode status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si sta 08h a start condition has been transmitted. load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received. 10h a repeat start condition has been transmitted. load sla+r or x 0 0 x as above load sla+w sla+w will be transmitted; i 2 c-bus will be switched to master transmitter mode. 38h arbitration lost in not ack bit. no s1dat action or 000xi 2 c-bus will be released; it will enter a slave mode. no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free. 40h sla+r has been transmitted; ack has been received. no s1dat action or 0 0 0 0 data byte will be received; not ack bit will be returned. no s1dat action or 0 0 0 1 data byte will be received; ack bit will be returned. 48h sla+r has been transmitted; not ack has been received. no s1dat action or 1 0 0 x repeated start will be transmitted. no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no s1dat action or 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 35 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 50h data byte has been received; ack has been returned. read data byte 0 0 0 0 data byte will be received; not ack bit will be returned. read data byte 0 0 0 1 data byte will be received; ack bit will be returned. 58h data byte has been received; not ack has been returned. read data byte or 1 0 0 x repeated start will be transmitted. read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset. read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. table 23. master receiver mode ?continued status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si sta table 24. slave receiver mode status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa 60h own sla+w has been received; ack has been received. no s1dat action or x000data byte will be received and not ack will be returned. no s1dat action x001data byte will be received and ack will be returned. 68h arbitration lost in sla+r/was master; own sla+w has been received, ack returned. no s1dat action or x000data byte will be received and not ack will be returned. no s1dat action x001data byte will be received and ack will be returned. 70h general call address(00h) has been received, ack has been returned. no s1dat action or x000data byte will be received and not ack will be returned. no s1dat action x001data byte will be received and ack will be returned. 78h arbitration lost in sla+r/w as master; general call address has been received, ack bit has been returned. no s1dat action or x000data byte will be received and not ack will be returned. no s1dat action x001data byte will be received and ack will be returned. 80h previously addressed with own sla address; data has been received; ack has been returned. read data byte orx000data byte will be received and not ack will be returned. read data bytex001data byte will be received; ack bit will be returned.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 36 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 88h previously addressed with own sla address; data has been received; not ack has been returned. read data byte or0000switched to not addressed sla mode; no recognition of own sla or general address. read data byte or 0001switched to not addressed sla mode; own sla will be recognized; general call address will be recognized if s1adr.0 = 1. read data byte or 1000switched to not addressed sla mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte1001switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data has been received; ack has been returned. read data byte orx000data byte will be received and not ack will be returned. read data bytex001data byte will be received and ack will be returned. 98h previously addressed with general call; data has been received; not ack has been returned. read data byte0000switched to not addressed sla mode; no recognition of own sla or general call address. read data byte0001switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. read data byte1000switched to not addressed sla mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte1001switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. a start condition will be transmitted when the bus becomes free. table 24. slave receiver mode ?continued status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 37 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi a0h a stop condition or repeated start condition has been received while still addressed as sla/rec or sla/trx. no s1dat action0000switched to not addressed sla mode; no recognition of own sla or general call address. no s1dat action0001switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. no s1dat action1000switched to not addressed sla mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no s1dat action1001switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. a start condition will be transmitted when the bus becomes free. table 24. slave receiver mode ?continued status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa table 25. slave transmitter mode status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa a8h own sla+r has been received; ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack will be received. b0h arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack bit will be received. b8h data byte in s1dat has been transmitted; ack has been received. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received load data byte x 0 0 1 data byte will be transmitted; ack will be received.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 38 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.5 timers/counters 0 and 1 the two 16-bit timer/counter registers: timer 0 and timer 1 can be configured to operate either as timers or event counters (see ta b l e 2 6 and ta b l e 2 7 ). in the ?timer? function, the register is in cremented every machine cycle. thus, one can think of it as counting machine cycles. sinc e a machine cycle consists of six oscillator periods, the count rate is 1 6 of the oscillator frequency. c0h data byte in s1dat has been transmitted; not ack has been received. no s1dat action or 0 0 0 0 switched to not addressed sla mode; no recognition of own sla or general call address. no s1dat action or 0 0 0 1 switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. no s1dat action or 1 0 0 0 switched to not addressed sla mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no s1dat action 1 0 0 1 switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been transmitted (aa = 0); ack has been received. no s1dat action or 0 0 0 0 switched to not addressed sla mode; no recognition of own sla or general call address. no s1dat action or 0 0 0 1 switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. no s1dat action or 1 0 0 0 switched to not addressed sla mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no s1dat action 1 0 0 1 switched to not addressed sla mode; own slave address will be recognized; general call address will be recognized if s1adr.0 = 1. a start condition will be transmitted when the bus becomes free. table 25. slave transmitter mode ?continued status code (s1sta) status of the i 2 c-bus hardware application software response next action taken by i 2 c-bus hardware to/from s1dat to s1con sta sto si aa
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 39 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in the ?counter? function, the register is increm ented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register in the machine cycle following the one in which the transition was detected. since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1 12 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. in addition to the ?timer? or ?counter? selection, timer 0 and timer 1 have four operating modes from which to select. the ?timer? or ?counter? function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. table 26. tmod - timer/counte r mode control register (address 89h) bit allocation not bit addressable; reset value: 0000 0000b; reset source(s): any source bit 7 6 5 4 3 2 1 0 symbol t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 table 27. tmod - timer/counter mode control register (address 89h) bit description bit symbol description 7 t1gate gating control for timer 1. when set, timer/counter is enabled only while the int1 pin is high and the tr1 control pin is set. when cleared, timer 1 is enabled when the tr1 control bit is set. 6t1c/t timer or counter select for timer 1. cleared for timer operation (input from cclk). set for counter operation (input from t1 input pin). 5 t1m1 mode select for timer 1. 4t 1 m 0 3 t0gate gating control for timer 0. when set, timer/counter is enabled only while the int0 pin is high and the tr0 control pin is set. when cleared, timer 0 is enabled when the tr0 control bit is set. 2t0c/t timer or counter select for timer 0. cleared for timer operation (input from cclk). set for counter operation (input from t0 input pin). 1 t0m1 mode select for timer 0. 0t 0 m 0 table 28. tmod - timer/counter mode control register (address 89h) m1/m0 operating mode m1 m0 operating mode 0 0 0 8048 timer ?tlx? serves as 5-bit prescaler. 0 1 1 16-bit timer/counter ?thx? and ?tlx' are cascaded; there is no prescaler.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 40 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.5.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a fixed divide-by-32 prescaler. figure 14 shows mode 0 operation. 1 0 2 8-bit auto-reload timer/counter ?thx? holds a value which is to be reloaded into ?tlx? each time it overflows. 1 1 3 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 3 (timer 1) timer/counter 1 stopped. table 29. tcon - timer/counter control register (address 88h) bit allocation bit addressable; reset value: 0000 0000b; reset source(s): any reset bit 7 6 5 4 3 2 1 0 symbol tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 30. tcon - timer/counter control register (address 88h) bit description bit symbol description 7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the proces sor vectors to timer 1 interrupt routine, or by software. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. 5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the proces sor vectors to timer 0 interrupt routine, or by software. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off. 3 ie1 interrupt 1 edge flag. set by hardware when external interrupt 1 edge/low-state is detected. cleared by hardware when the interrupt is processed, or by software. 2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low-state that triggers external interrupt 1. 1 ie0 interrupt 0 edge flag. set by hardware when external interrupt 0 edge/low-state is detected. cleared by hardware when the interrupt is processed, or by software. 0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low-state that triggers external interrupt 0. table 28. tmod - timer/counter mode control register (address 89h) m1/m0 operating mode ?continued m1 m0 operating mode
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 41 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer inte rrupt flag tfn. the count input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements) . trn is a control bit in the special function register tcon ( figure 5 ). the gate bit is in the tmod register. the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 and timer 1 (see figure 14 ). there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). 6.5.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register (thn and tln) are used. see figure 15 . 6.5.3 mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 16 . overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which must be preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 and timer 1. fig 14. timer/counter 0 or 1 in mode 0 (13-bit counter) 002aaa519 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (5-bits) thn (8-bits) tfn control overflow interrupt fig 15. timer/counter 0 or 1 in mode 1 (16-bit counter) 002aaa520 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (8-bits) thn (8-bits) tfn control overflow interrupt
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 42 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.5.4 mode 3 when timer 1 is in mode 3 it is stopped (holds its count). the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate 8-bit counters. the logic for mode 3 and timer 0 is shown in figure 17 . tl0 uses the timer 0 control bits: t0c/t , t0gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf 1 from timer 1. thus, th0 now controls the ?timer 1? interrupt. mode 3 is provided for applications that re quire an extra 8-bit timer. with timer 0 in mode 3, the p89v660/662/664 can look like it has an additional timer. note: when timer 0 is in mode 3, timer 1 can be turned on and off by switching it into and out of its own mode 3. it can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. 6.6 timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t 2 in the special function register t2con. timer 2 has four operating modes: capture, auto-reload (up or down counting), clock-out, and baud rate generator which are selected according to ta b l e 3 1 using t2con ( ta b l e 3 2 and ta b l e 3 3 ) and t2mod ( ta b l e 3 4 and ta b l e 3 5 ). fig 16. timer/counter 0 or 1 in mode 2 (8-bit auto-reload) 002aaa521 osc/6 tn pin trn tngate intn pin tln (8-bits) thn (8-bits) tfn control overflow reload interrupt c/t = 0 c/t = 1 fig 17. timer/counter 0 mode 3 (two 8-bit counters) 002aaa522 osc/2 tr1 tr0 tngate int0 pin tl0 (8-bits) tf0 control overflow interrupt th0 (8-bits) tf1 control overflow interrupt osc/6 t0 pin c/t = 0 c/t = 1
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 43 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 31. timer 2 operating mode rclk+tclk cp/rl 2 tr2 t2oe mode 0 0 1 0 16-bit auto reload 0 1 1 0 16-bit capture 0 0 1 1 programmable clock-out 1 x 1 0 baud rate generator xx0 xoff table 32. t2con - timer/counter 2 control register (address c8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol tf2 exf2 rclk tclk exen2 tr2 c/t 2cp/rl 2 table 33. t2con - timer/counter 2 control re gister (address c8h) bit description bit symbol description 7 tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1 or when timer 2 is in clock-out mode. 6 exf2 timer 2 external flag is set when timer 2 is in capture, reload or baud rate mode, exen2 = 1 and a negative transition on t2ex occurs. if timer 2 interrupt is enabled exf2 = 1 causes the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. 5 rclk receive clock flag. when set, causes the uart to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. 4 tclk transmit clock flag. when set, causes the uart to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. 3 exen2 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2. a logic ?1? enables the timer to run. 1c / t 2 timer or counter select. (timer 2) 0 = internal timer (f osc /6) 1 = external event counter (falling edge triggered; external clock?s maximum rate = f osc / 12. 0cp/rl 2 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflow s or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. table 34. t2mod - timer 2 mode control register (address c9h) bit allocation not bit addressable; reset value: xx00 0000b bit 7 6 5 4 3 2 1 0 symbol ------t2oedcen
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 44 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.6.1 capture mode in the capture mode there ar e two options which are select ed by bit exen2 in t2con. if exen2 = 0 timer 2 is a 16-bit timer or counter (as se lected by c/t 2 in t2con) which upon overflowing sets bit tf2, the timer 2 overflow bit. the capture mode is illustrated in figure 18 . this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ien0 register). if exen2 = 1, timer 2 operates as described above, but with the added feature that a 1- to -0 tran sition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt). the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt. there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2 pin transitions or f osc / 6 pulses. since once loaded contents of rcap2l and rcap2h registers are not protected, once timer2 interrupt is signalled it has to be serviced before new capture event on t2ex pin occurs. otherwise, the next falling edge on t2ex pin will initiate relo ad of the curren t value from tl2 and th2 to rcap2l and rcap2h and conseq uently corrupt their content related to previously reported interrupt. table 35. t2mod - timer 2 mode control register (address c9h) bit description bit symbol description 7 to 2 - reserved for future use. should be set to ?0? by user programs. 1 t2oe timer 2 output enable bit. us ed in programmable clock-out mode only. 0 dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down-counter. fig 18. timer 2 in capture mode 002aaa523 osc 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control capture tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 45 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.6.2 auto-reload mode (up or down-counter) in the 16-bit auto-reload mode, timer 2 can be configured as either a timer or counter (via c/t 2 in t2con), then programmed to count up or down. the counting direction is determined by bit dcen (down-counter enable) which is located in the t2mod register (see table 34 and ta b l e 3 5 ). when reset is applied, dc en = 0 and timer 2 will default to counting up. if the dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 19 shows timer 2 counting up automatically (dcen = 0). in this mode, there are two options sele cted by bit exen2 in t2con register. if exen2 = 0, then timer 2 counts up to 0ffffh and se ts the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap 2l and rcap2h are preset by software means. auto reload frequency when timer 2 is counting up can be determined from this formula: (1) where supplyfrequency is either f osc (c/t2 = 0) or frequency of signal on t2 pin (c/t2 =1). if exen2 = 1, a 16-bit reload ca n be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 is ?1?. microcontroller?s hardware w ill need three consecutive ma chine cycles in order to recognize falling edge on t2ex and set exf2 = 1: in the first machine cycle pin t2ex has to be sampled as ?1?; in the second machine cycle it has to be sampled as ?0?, and in the third machine cycle exf2 will be set to ?1?. fig 19. timer 2 in auto-reload mode (dcen = 0) 002aaa524 osc 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control reload tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin supplyfrequency 65536 rcap2h rcap2l ? ?? ? --------------------------------------------------------------------------- -
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 46 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in figure 20 , dcen = 1 and timer 2 is enabled to count up or down. this mode allows pin t2ex to control the direction of count. when a logic ?1? is applied at pin t2ex timer 2 will count up. timer 2 will overflow at 0ffffh a nd set the tf2 flag, wh ich can then generate an interrupt, if th e interrupt is enabled. this timer over flow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. 6.6.3 programmable clock-out a 50 % duty cycle clock can be programmed to come out on pin t2 (p1[0]). this pin, besides being a regular i/o pin, has two additional functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50 % duty cycle clock rang ing from 122 hz to 8 mhz at a 16 mhz operating frequency. to configure the timer/counter 2 as a clock generator, bit c/t 2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in equation 2 : (2) where n = 2 (6-clock mode) and n = 4 (12-clock mode); where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. fig 20. timer 2 in auto reload mode (dcen = 1) 002aaa525 tl2 (8-bits) th2 (8-bits) tf2 exf2 underflow timer 2 interrupt rcap2l rcap2h ffh ffh overflow (down-counting reload value) (up-counting reload value) count direction 1 = up 0 = down t2ex pin toggle osc 6 t2 pin c/t2 = 0 c/t2 = 1 control tr2 oscillatorfrequency n 65536 rcap2h rcap2l ? ?? ? ?? ? ----------------------------------------------------------------------------------------- -
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 47 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in the clock-out mode timer 2 ro llovers will not generate an inte rrupt. this is similar to when it is used as a baud rate generator. 6.6.4 baud rate generator mode bits tclk and/or rclk in t2con allow the ua rt) transmit and receive baud rates to be derived from either timer 1 or timer 2 (see section 6.7 for details). when tclk = 0, timer 1 is used as the uart transmit baud rate generator. when tclk = 1, timer 2 is used as the uart transmit baud rate generator. rclk has the same effect for the uart receive baud rate. with these two bits, the se rial port can have different receive and transmit baud rates ? timer 1 or timer 2. figure 21 shows timer 2 in baud rate generator mode: the baud rate generation mode is like the auto-reload mode, when a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2?s overflow rate given below: modes 1 and 3 baud rates = timer 2 overflow rate / 16 the timer can be configured for either ?timer? or ?counter? operation. in many applications, it is configured for ?timer' operation (c/t 2 = 0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1 6 the oscillator frequency). as a baud rate generator, it incr ements at the oscillato r frequency. thus the baud rate formula is as follows: modes 1 and 3 baud rates = (3) where k = 16 (6-clock mode) and k = 32 (12-clock mode); where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. fig 21. timer 2 in baud rate generator mode 002aaa526 tx/rx baud rate timer 2 interrupt osc 2 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) control tr2 exf2 rcap2l rcap2h control exen2 transition detector t2ex pin reload oscillatorfrequency k 65536 rcap2h rcap2l ? ?? ?? ? ---------------------------------------------------------------------------------------
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 48 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi the timer 2 as a baud rate generator mode is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th 2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/coun ter 2 trigger input) will set exf 2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. ta b l e 3 6 shows commonly used baud rates and how they can be obtained from timer 2. 6.6.5 summary of baud rate equations timer 2 is in baud rate generating mode. if ti mer 2 is being clocked through pin t2 (p1[0]) the baud rate is: baud rate = timer 2 overflow rate / 16 if timer 2 is being clocked internally, the baud rate is: baud rate = f osc /(16 ? (65536 ? (rcap2h, rcap2l))) where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l = 65536 ? f osc /(16 ? baud rate) 6.7 uarts the uart operates in all standard modes. enhancements over the standard 80c51 uart include framing error detection, and automatic address recognition. table 36. timer 2 generated commonly used baud rates rate oscillator frequency timer 2 rcap2h rcap2l 750 kbd 12 mhz ff ff 19.2 kbd 12 mhz ff d9 9.6 kbd 12 mhz ff b2 4.8 kbd 12 mhz ff 64 2.4 kbd 12 mhz fe c8 600 bd 12 mhz fb 1e 220 bd 12 mhz f2 af 600 bd 6 mhz fd 8f 220 bd 6 mhz f9 57
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 49 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.7.1 mode 0 serial data enters and exits through rxd and txd outputs the shift clock. only 8 bits are transmitted or received, lsb first. the baud rate is fixed at 1 6 of the cpu clock frequency. uart configured to operate in this mode outputs serial clock on txd line no matter whether it sends or receives data on rxd line. 6.7.2 mode 1 10 bits are transmitted (through txd) or receiv ed (through rxd): a start bit (logical 0), 8 data bits (lsb first), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 2 overflow rate. 6.7.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (logical 1). when data is transmitted, the 9th data bit (tb8 in scon) can be assigned the value of 0 or (e.g. the parity bit (p, in the psw) could be moved into tb8). when data is received, the 9th data bit goes into rb8 in special function regist er scon, while the stop bit is ignored. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 6.7.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb first), a programmable 9th data bi t, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 2 overflow rate. table 37. scon - serial port control register (address 98h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol sm0/fe sm1 sm2 ren tb8 rb8 ti ri table 38. scon - serial port control register (address 98h) bit description bit symbol description 7 sm0/fe the usage of this bit is determined by smod0 in the pcon register. if smod0 = 0, this bit is sm0, which with sm1, defines the serial port mode. if smod0 = 1, this bit is fe (framing error). fe is set by the receiver when an invalid stop bit is detected. once set, this bit cannot be cleared by valid frames but can only be cleared by software. (note: it is recommended to set up uart mode bits sm0 and sm1 before setting smod0 to ?1?.) 6 sm1 with sm0, defines the serial port mode (see ta b l e 3 9 below). 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to ?1 ?, then rl will not be activated if the received 9th data bit (rb8) is ?0?. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit wa s not received. in mode 0, sm2 should be ?0?. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 50 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.7.5 framing error framing error (fe) is reported in the scon.7 bit if smod0 (pcon.6) = 1. if smod0 = 0, scon.7 is the sm0 bit for the uart, it is recommended that sm0 is set up before smod0 is set to ?1?. 6.7.6 more about uart mode 1 reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit det ector samples the value of rxd. the value accepted is the value that was seen in at leas t 2 of the 3 samples. this is done for noise rejection. if the value accepted during the firs t bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit pr oves valid, it is shifted into the input shift register, and receptio n of the rest of the frame will proceed. the signal to load sbuf and rb8, and to set ri, will be gene rated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb 8, the 8 data bits go into sbuf, and ri is activated. 6.7.7 more about uart modes 2 and 3 reception is performed in the same manner as in mode 1. 3 tb8 the 9th data bit that will be transmitt ed in modes 2 and 3. set or clear by software as desired. 2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is undefined. 1 ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the stop bit in the other modes, in any serial transmission. must be cleared by software. 0 ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or approxim ately halfway through the stop bit time in all other modes. (see sm2 for exceptions). must be cleared by software. table 39. scon - serial port control regi ster (address 98h) sm0/sm1 mode definition sm0, sm1 uart mode baud rate 0 0 0: shift register cpu clock / 6 0 1 1: 8-bit uart variable 1 0 2: 9-bit uart cpu clock / 32 or cpu clock / 16 1 1 3: 9-bit uart variable table 38. scon - serial port control register (address 98h) bit description ?continued bit symbol description
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 51 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi the signal to load sbuf and rb8, and to set ri, will be gene rated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the rece ived frame is irretrievabl y lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. 6.7.8 multiprocessor communications uart modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received or transm itted. when data is received, the 9th bit is stored in rb8. the uart can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if rb 8 = 1. this feature is enabled by setting bit sm2 in scon. one way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifie s the target slave. an address byte differs from a data byte in a way that the 9th bit is ?1? in an address byte and ?0? in the data byte. with sm2 = 1, no slave will be in terrupted by a data by te, i.e. the received 9th bit is ?0?. however, an address byte having th e 9th bit set to ?1? will interr upt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. the addressed slave will clear its sm2 bit and prepare to receive the data (still 9 bits long) that follow. the slaves that weren?t being addressed leave their sm2 bits set and go on about their business, ignoring the subsequent data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the fram ing error flag. when uart receives data in mode 1 and sm2 = 1, th e receive interrupt will not be activated unless a valid stop bit is received. 6.7.9 automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by usi ng hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled for the uart by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (r i) will be automatically set when the received byte contains either the ?given? address or the ?broadcast' address. the 9 bit mode requires that the 9th information bit is a ?1? to indicate that the received information is an address and not data. using the automatic address recognition f eature allows a master to selectively communicate with one or more slaves by invo king the given slave address or addresses. all of the slaves may be contacted by usin g the broadcast address. two special function registers are used to define the slave?s address, saddr, and the address mask, saden. saden is used to define which bits in the sa ddr are to be used and which bits are ?don?t care?. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressi ng each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. this device uses the methods presented in figure 22 to determine if a given or broadcast address has been received or not.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 52 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi the following examples will help to sh ow the versatility of this scheme. example 1, slave 0: (4) example 2, slave 1: (5) in the above example saddr is the same an d the saden data is used to differentiate between the two slaves. slave 0 requires a ?0? in bit 0 and it ignores bit 1. slave 1 requires a ?0? in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a ?0? in bit 1. a unique address for slave 1 would be 1100 0001 since a ?1? in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (f or slave 1). thus, both could be addressed with 1100 0000. fig 22. schemes used by the uart to dete ct ?given? and ?broadcast? addresses when multiprocessor communications is enabled 002aaa527 rx_byte(7) saddr(7) saden(7) rx_byte(0) saddr(0) . . . given_address_match logic used by uart to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) saddr(0) saden(0) rx_byte(0) broadcast_address_match logic used by uart to detect 'given address' in received data saden(0) . . . saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1110 given = 1100 000x --------------------------------------------------- -
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 53 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: example 1, slave 0: (6) example 2, slave 1: (7) example 2, slave 2: (8) in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is ne cessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as do n?t-cares. in most ca ses, interpreting the don?t-cares as ones, the br oadcast address will be ff hex adecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all ?don?t cares? as well as a broadcast address of all ?don?t cares' . this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. 6.8 serial peripheral interface (spi) 6.8.1 spi features ? master or slave operation ? 10 mhz bit frequency (max) ? lsb first or msb first data transfer ? four programmable bit rates ? end of transmission (spif) ? write collision flag protection (wcol) ? wake-up from idle mo de (slave mode only) 6.8.2 spi description the serial peripheral interface allows high-speed synchronous data transfer between the p89v660/662/664 and peripheral devices or between several p89v660/662/664 devices. figure 23 shows the correspondence between master and slave spi devices. the saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 --------------------------------------------------- - saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1100 given = 1100 00xx --------------------------------------------------- -
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 54 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi spiclk pin is the clock output and input for the master and slave modes, respectively. the spi clock generator will start following a writ e to the master devices spi data register. the written data is then shifted out of the mosi pin on the master device into the mosi pin of the slave device. following a complete transmission of one byte of data, the spi clock generator is stopped and the spif flag is set. an spi interrupt request will be generated if the spi interrupt enable bit (spie) and the spi interrupt enable bit, es3, are both set. an external master drives t he slave select input pin, ss low to select the spi module as a slave. if ss has not been driven low, then the slav e spi unit is not active and the mosi pin can also be used as an input port pin. cpha and cpol control the phase and polarity of the spi clock. figure 24 and figure 25 show the four possible combinations of these two bits. fig 23. spi master-slave interconnection 002aaa528 8-bit shift register msb master lsb spi clock generator miso miso mosi mosi spiclk spiclk ss ss 8-bit shift register msb slave lsb v ss v dd table 40. spcr - spi control register (address d5h) bit allocation bit addressable; reset source(s): any reset; reset value: 0000 0000b bit 7 6 5 4 3 2 1 0 symbol spie spen dord mstr cpol cpha spr1 spr0 table 41. spcr - spi control register (address d5h) bit description bit symbol description 7 spie if both spie and es3 are set to one, spi interrupts are enabled. 6 spen spi enable bit. when set enables spi. 5 dord data transmission order. 0 = msb first; 1 = lsb first in data transmission. 4 mstr master/slave select. 1 = master mode, 0 = slave mode. 3 cpol clock polarity. 1 = spiclk is high when idle (active low), 0 = spiclk is low when idle (active high).
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 55 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 2 cpha clock phase control bit. 1 = shift triggered on the trailing edge of the clock; 0 = shift triggered on the leading edge of the clock. 1 spr1 spi clock rate select bit 1. along with spr0 controls the spiclk rate of the device when a master. spr1 and spr0 have no effect on the slave. see ta b l e 4 2 . 0 spr0 spi clock rate select bit 0. along with spr1 controls the spiclk rate of the device when a master. spr1 and spr0 have no effect on the slave. see ta b l e 4 2 . table 42. spcr - spi control register (address d5h) clock rate selection spr1 spr0 spiclk = f osc divided by 6-clock mode 12-clock mode 002 4 018 16 1032 64 1164 128 table 43. spsr - spi status register (address aah) bit allocation bit addressable; reset source(s): any reset; reset value: 0000 0000b bit 7 6 5 4 3 2 1 0 symbol spif wcol - - - - - - table 44. spsr - spi status register (address aah) bit description bit symbol description 7 spif spi interrupt flag. upon completion of data transfer, this bit is set to ?1?. if spie = 1 and es3 = 1, an interrupt is then generated. this bit is cleared by software. 6 wcol write collision flag. set if the spi data register is written to during data transfer. this bit is cleared by software. 5 to 0 - reserved for future use. should be set to ?0? by user programs. fig 24. spi transfer format with cpha = 0 table 41. spcr - spi control register (address d5h) bit description ?continued bit symbol description 002aaa529 spiclk cycle # (for reference) spiclk (cpol = 0) spiclk (cpol = 1) mosi (from master) miso (from slave) ss (to slave) 12345678 msb 6 5 4 3 2 1 lsb msb 654321lsb
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 56 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.9 watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is disabl ed at reset. to enable the wdt, the user must write 01eh and 0e1h, in sequence, to the wdtrst sfr. when the wdt is enabled, it will increment every machine cycle while the oscilla tor is running and there is no way to disable the wdt, except through a reset (either hardware reset or a wdt overflow reset). when the wdt overflows, it will drive an output reset high pulse at the rst pin. when the wdt is enabled (and thus running) th e user needs to reset it by writing 01eh and 0e1h, in sequence, to the wdtrst sfr to avoid wdt overflow. the 14-bit counter reaches overflow when it reaches 16383 (3f ffh) and this will reset the device. the wdt?s counter cannot be read or written. when the wdt overflows it will generate a output pulse at the reset pin with a duration of 98 oscillator periods in 6 clock mode or 196 oscillator periods in 12 clock mode. 6.10 pca the pca includes a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling e dge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it. module 0 is connected to cex0, module 1 to cex1, etc. registers ch and cl contain current value of the free running up counting 16-bit pca timer. the pc a timer is a common time base for all five modules and can be programmed to run at: 1 6 the oscillator frequency, 1 2 the oscillator frequency, the timer 0 overflow, or the inpu t on the eci pin (p1[2]). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 45 and ta b l e 4 6 ). fig 25. spi transfer format with cpha = 1 002aaa530 msb s picl k cycle # (for reference) s picl k (cpol = 0) s picl k (cpol = 1) mosi (from master) miso (from slave) ss (to slave) 6 12345678 5 msb 6 5 4 3 2 1 lsb 4 3 2 1 lsb
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 57 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi in the cmod sfr there are three additional bi ts associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the watchdog timer function is implemented in module 4 of pca. the ccon sfr contains the run control bit for the pca (cr) and the flags for the pca timer (cf) and each module (ccf4:0). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing th is bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be clear ed by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags can only be cleared by software. all the modules share one interrupt vector. the pca interrupt system is shown in figure 27 . each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. the registers contain the bits that control the mode that each module will operate in. the eccf bit (from ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccfn flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module (see figure 27 ). pwm (ccapmn.1) enables the pu lse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module?s capture/compare register. the match bit mat (ccapmn.3) when set will caus e the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module?s capture/compare register. fig 26. pca module0 pca timer/counter p1[3]/cex0 module1 p1[4]/cex1 module2 p1[5]/cex2 module3 p1[6]/cex3 module4 p1[7]/cex4 time base for pca modules module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit pwm - watchdog timer (module 4 only) 16 bits 16 bits 002aab913
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 58 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi the next two bits capn (cc apmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bi t enables the negative edge, and the capp bit enables the positive edge. if both bits ar e set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. there are two additional regi sters associated with each of the pca modules. they are ccapnh and ccapnl and these are the regist ers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are us ed to control the duty cycle of the output. fig 27. pca interrupt system 002aab914 pca timer/counter module0 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 module1 module2 module3 module4 ecf eccfn ien0.6 ec ien0.7 ea ccapmn.0 cmod.0 ccon (c0h) to interrupt priority decoder table 45. cmod - pca counter mode register (address c1h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol cidl wdte - - - cps1 cps0 ecf
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 59 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 46. cmod - pca counter mode register (address c1h) bit description bit symbol description 7 cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. 6 wdte watchdog timer enable: wdte = 0 disables watchdog timer function on module 4. wdte = 1 enables it. 5 to 3 - reserved for future use. should be set to ?0? by user programs. 2 to 1 cps1, cps0 pca count pulse select (see table 47 below). 0 ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function. table 47. cmod - pca counter mode register (address c1h) count pulse select cps1 cps0 select pca input 0 0 0 internal clock, f osc /6 0 1 1 internal clock, f osc /6 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p1[2] pin (max rate = f osc /4) table 48. ccon - pca counter control regi ster (address 0c0h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 table 49. ccon - pca counter control regi ster (address 0c0h) bit description bit symbol description 7 cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. 6 cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. 5 - reserved for future use. should be set to ?0? by user programs. 4 ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 3 ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 2 ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 1 ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 0 ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 60 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.10.1 pca capture mode to use one of the pca modules in the capture mode ( figure 28 ) either one or both of the ccapm bits capn and capp for that module must be set. th e external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module?s capture registers (ccapnl and ccapnh). table 50. ccapmn - pca modules compare/ca pture register (address ccapm0 0c2h, ccapm1 0c3h, ccapm2 0c4h, ccapm3 0c5h, ccapm4 0c6h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - ecomn cappn capnn matn togn pwmn eccfn table 51. ccapmn - pca modules compare/ca pture register (address ccapm0 0c2h, ccapm1 0c3h, ccapm2 0c4h, ccapm3 0c5h, ccapm4 0c6h) bit description bit symbol description 7 - reserved for future use. should be set to ?0? by user programs. 6 ecomn enable comparator. ecomn = 1 enables the comparator function. 5 cappn capture positive, cappn = 1 enables positive edge capture. 4 capnn capture negative, capnn = 1 enables negative edge capture. 3 matn match. when matn = 1 a match of the pca counter with this module?s compare/capture register causes th e ccfn bit in ccon to be set, flagging an interrupt. 2 togn toggle. when togn = 1, a match of the pca counter with this module?s compare/capture register causes the cexn pin to toggle. 1 pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. 0 eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. table 52. pca module mo des (ccapmn register) ecomn cappn capnn matn togn pwmn eccfn module function 0000000no operation x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x 0 1 0 0 0 x 16-bit capture by a negative-edge trigger on cexn x 1 1 0 0 0 x 16-bit capture by any transition on cexn 100100x16-bit software timer 1 0 0 1 1 0 x 16-bit high-speed output 10000108-bit pwm 1 0 0 1 x 0 x watchdog timer
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 61 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an inte rrupt will be generated. 6.10.2 16-bit software timer mode the pca modules can be used as software timers ( figure 29 ) by setting both the ecom and mat bits in the modules ccapmn regist er. the pca timer will be compared to the module?s capture registers an d when a match occurs an in terrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set. fig 28. pca capture mode 002aab915 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) pca interrupt pca timer/counter - ecomn 0000 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (c2h to c6h) ch cl ccapnh ccapnl capture (to ccfn) cexn
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 62 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.10.3 high-speed output mode in this mode ( figure 30 ) the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module?s capture registers. to activate this mode the tog, mat, and ecom bits in the module?s ccapmn sfr must be set. fig 29. pca compare mode 002aab916 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) pca interrupt - ecomn 00 100 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (c2h to c6h) 16-bit comparator pca timer/counter ch cl match (to ccfn) ccapnh ccapnl enable write to ccapnh write to ccapnl reset 01
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 63 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.10.4 pulse width modulator mode all of the pca modules can be used as pwm outputs ( figure 31 ). output frequency depends on the source for the pca timer. all of the modules will have t he same frequency of output because they all share one and only pca timer. the duty cycle of each mo dule is independently variable using the module?s capture register ccapnl. when the value of the pca cl sfr is less than the fig 30. pca high-speed output mode 002aab917 toggle cexn cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) pca interrupt - ecomn 00 100 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (c2h to c6h) 16-bit comparator pca timer/counter ch cl match (to ccfn) ccapnh ccapnl enable write to ccapnh write to ccapnl reset 01 fig 31. pca pwm mode 002aab918 - ecomn 0 100011 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (c2h to c6h) ccapnl 8-bit comparator pca timer/counter ccapnh cl enable cexn cl < ccapnl cl ccapnl 0 1
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 64 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi value in the module?s ccapnl sf r the output will be low, when it is equal to or greater than the output will be high. w hen cl overflows from ff to 00, ccapnl is reloaded with the value in ccapnh. this allows updatin g the pwm without glitches. the pwm and ecom bits in the module?s ccapmn register must be set to enable the pwm mode. 6.10.5 pca watchdog timer an on-board watchdog timer is available with the pca to im prove the reliability of the system without increasing chip count. watchdo g timers are useful for systems that are susceptible to noise, power glitches, or elec trostatic discharge. module 4 is the only pca module that can be pr ogrammed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 31 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not ca use the rst pin to be driven high. user?s software then must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine shown above. in order to hold off the reset, the user has three options: 1. periodically change th e compare value so it will never match the pca timer. 2. periodically change the pc a timer value so it will never match the compare values. 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second optio n is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. ;call the following watchdog subroutine periodically. clr ea ;hold off interrupts mov ccap4l,#00 ;next compare value is within 255 counts of current pca timer value mov ccap4h,ch setb ea ;re-enable interrupts ret this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus , the purpose of th e watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 65 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.11 security bits the security bits protects against software piracy and prevents the contents of the flash from being read by unauthorized parties in parallel programmer mode and isp mode. since the end application might need to erase pages and read from the code memory, the security bits have no effect in iap mode. however, the security bits? programmed/erased state may be read using iap function calls a llowing the end user code to limit access, if desired. the security bits and their effects are shown in ta b l e 5 3 . note: on this device movc instructions executed from external code memory are disabled from fetching code bytes from internal code memory. 6.12 interrupt priority and polling sequence the device supports eight interrupt sources under a four level priority scheme. ta b l e 5 4 summarizes the polling sequence of the supported interrupts. note that the spi serial interface and the uart share the same interrupt vector. (see figure 32 ). table 53. security bit functions security bit description 1 write protect. when programmed, prohibits further erasing or programming, except to program other security bits or a chip erase. 2 read protect. when programmed inhibits reading of user code memory. 3 external execution inhibit. when pr ogrammed prevents any execution of instructions from external code memory. table 54. interrupt polling sequence description interrupt flag vector address interrupt enable interrupt priority service priority wake-up power-down external interrupt 0 ie0 0003h ex0 px0/h 1 (highest) yes t0 tf0 000bh et0 pt0/h 3 no external interrupt 1 ie1 0013h ex1 px1/h 4 yes t1 tf1 001bh et1 pt1/h 5 no uart ti/ri 0023h es0 ps0/h 6 no i 2 c-bus (primary) - 002bh es1 ps1/h 2 no pca cf/ccfn 0033h ec ppch 8 no t2 tf2, exf2 003bh et2 pt2/h 7 no i 2 c-bus (secondary) - 0043h es2 ps2/h 10 no spi spif 004bh es3 ps3/h 9 no
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 66 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 32. interrupt structure 002aab919 highest priority interrupt interrupt polling sequence int0 ie and iea registers ip/iph/ipa/ipah registers individual enables global disable ie0 0 1 it0 lowest priority interrupt spie spif tf0 int1 tf1 cf ecf ccfn eccfn ri ti tf2 exf2 i 2 c-bus (primary) i 2 c-bus (secondary) ie1 0 1 it1
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 67 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 55. ien0 - interrupt enable regi ster 0 (address a8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol ea ec es1 es0 et1 ex1 et0 ex0 table 56. ien0 - interrupt enable register 0 (address a8h) bit description bit symbol description 7 ea interrupt enable bit: ea = 1 interrupt(s) can be serviced, ea = 0 interrupt servicing disabled. 6 ec pca interrupt enable bit. 5es1i 2 c-bus interrupt enable (primary). 4 es0 serial port interrupt enable 3 et1 timer 1 overflow interrupt enable. 2 ex1 external interrupt 1 enable. 1 et0 timer 0 overflow interrupt enable. 0 ex0 external interrupt 0 enable. table 57. ien1 - interrupt enable register 1 (address e8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - - - es3 es2 et2 table 58. ien1 - interrupt enable register 1 (address e8h) bit description bit symbol description 7 to 3 - reserved for future use. should be set to ?0? by user programs. 2 es3 spi interrupt enable. 1es2i 2 c-bus interrupt enable (secondary). 0 et2 timer 2 interrupt enable. table 59. ip0 - interrupt priority 0 low register (address b8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol pt2 ppc ps1 ps0 pt1 px1 pt0 px0 table 60. ip0 - interrupt priority 0 low re gister (address b8h) bit description bit symbol description 7 pt2 timer 2 interrupt priority low bit. 6 ppc pca interrupt priority low bit. 5ps1i 2 c-bus interrupt priority low bit. 4 ps0 serial port interru pt priority low bit. 3 pt1 timer 1 interrupt priority low bit. 2 px1 external interrup t 1 priority low bit. 1 pt0 timer 0 interrupt priority low bit. 0 px0 external interrup t 0 priority low bit.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 68 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.13 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see table 67 . table 61. ip0h - interrupt priority 0 high register (address b7h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol pt2h ppch ps1h ps0h pt1h px1h pt0h px0h table 62. ip0h - interrupt priority 0 high register (address b7h) bit description bit symbol description 7 pt2h timer 2 interrupt priority high bit. 6 ppch pca interrupt priority high bit. 5ps1hi 2 c-bus interrupt priori ty high bit (primary). 4 ps0h serial port interru pt priority high bit. 3 pt1h timer 1 interrupt priority high bit. 2 px1h external interrupt 1 priority high bit. 1 pt0h timer 0 interrupt priority high bit. 0 px0h external interrupt 0 priority high bit. table 63. ip1 - interrupt priority 1 register (address 91h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - - - - ps3 ps2 table 64. ip1 - interrupt priority 1 register (address 91h) bit description bit symbol description 7 to 2 - reserved for future use. should be set to ?0? by user programs. 1 ps3 spi interrupt priority low bit. 0ps2i 2 c-bus interrupt priority 1 low bit (secondary). table 65. ip1h - interrupt priority 1 high register (address 92h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - - - - ps3h ps2h table 66. ip1h - interrupt priority 1 high register (address 92h) bit description bit symbol description 7 to 2 - reserved for future use. should be set to ?0? by user programs. 1 ps3h spi interrupt priority high bit. 0ps2hi 2 c-bus interrupt priority high bit (secondary).
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 69 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.13.1 idle mode idle mode is entered setting the idl bit in the pcon register. in idle mode, the program counter is stopped. the system clock continues to run and all interrupts and peripherals remain active. the on-chip ram and the specia l function registers hold their data during this mode. the device exits idle mode through either a sy stem interrupt or a ha rdware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routin e, the interrupted program resumes execution beginning at the instruction immediately follo wing the instruction which invoked the idle mode. a hardware reset starts the de vice similar to a power-on reset. 6.13.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power-down, the minimum v dd level is 2.0 v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal restored to logic v ih , the interrupt service routine program execution resumes beginning at the instruction immediat ely following the instruction which invoked power-down mode. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). table 67. power-saving modes mode initiated by state of mcu exited by idle mode software (set idl bit in pcon) mov pcon, #01h clk is running. interrupts, serial port and timers/counters are active. program counter is stopped. ale and psen signals at a high-state during idle. all regi sters remain unchanged. enabled interrupt or ha rdware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. a hardware reset restarts the device similar to a power-on reset. power-down mode software (set pd bit in pcon) mov pcon, #02h clk is stopped. on-chip sram and sfr data is maintained. ale and psen signals at a low-state during power-down. external interrupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive interrupt or hardware reset. start of interrupt clears pd bit and exits power-down mode, after the isr reti instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. a hardware reset restarts the device similar to a power-on reset.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 70 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 6.14 system clock and clock options 6.14.1 clock input options and recommended capacitor values for the oscillator shown in figure 33 and figure 34 are the input and output of an internal inverting amplifier (xtal1, xtal 2), which can be configured for use as an on-ch ip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external osc illator may encoun ter a higher capacitive load at xtal1 due to interaction between the amplifie r and its feedback capacitanc e. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih specifications. resonator manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. c 1 and c 2 should be adjusted appropriately for each design. ta b l e 6 8 shows the typical values for c 1 and c 2 vs. resonator type for various frequencies 6.14.2 clock doubling option by default, the device runs at six clocks per machine cycle. the device may be run in 12 clocks per machine cycle mode by fl ash programming of the 6x/12x bit. table 68. recommended values for c 1 and c 2 by crystal type resonator c 1 =c 2 quartz 20 pf to 30 pf ceramic 40 pf to 50 pf fig 33. oscillator characteristics (using the on-chip oscillator) fig 34. oscillator characteri stics (external clock drive) 002aaa545 xtal2 xtal1 v ss c 1 c 2 002aaa546 xtal2 n.c. xtal1 external oscillator signal v ss
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 71 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 7. limiting values 8. static characteristics table 69. limiting values in accordance with the absolute ma ximum rating system (iec 60134). parameters are valid over operating temp erature range unless other wise specified. all volta ges are with respect to v ss unless otherwise noted. symbol parameter conditions min max unit t amb(bias) bias ambient temperature ? 55 +125 ?c t stg storage temperature ? 65 +150 ?c v i input voltage on ea pin to v ss ? 0.5 14 v v n voltage on any other pin except v ss , with respect to v dd ? 0.5 v dd + 0.5 v i ol(i/o) low-level output current per input/output pin -15ma p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w table 70. static characteristics t amb = ? 40 ? cto+85 ? c; v dd = 4.5 v to 5.5 v; v ss =0v symbol parameter conditions min typ max unit n endu(fl) endurance of flash memory jedec standard a117 [1] 10000 - - cycles t ret(fl) flash memory retention time jedec standard a103 [1] 100 - - years i latch i/o latch-up current jedec standard 78 [1] 100 + i dd -- ma v th(hl) high-low threshold vo ltage except scl, sda ? 0.5 - 0.2v dd ? 0.1 v v il low-level input voltage scl, sda ? 0.5 - 0.3v dd v v th(lh) low-high threshold voltage except scl, sda, xtal1, rst 0.2v dd +0.9 - v dd +0.5 v v ih high-level input voltage scl, sda 0.7v dd -v dd +0.5 v xtal1, rst 0.7v dd -6.0 v v ol low-level output voltage v dd = 4.5 v, except, psen , ale, scl, sda [2] [3] [4] i ol =1.6ma - - 0.4 v v dd = 4.5 v, ale, psen i ol = 3.2 ma - - 0.45 v v dd = 4.5 v, scl, sda i ol =3.0ma - - 0.4 v v oh high-level output voltage v dd = 4.5 v, ports 1, 2, 3, 4 [5] i oh = ? 30 ? av dd ? 0.7 - - v v dd =4.5v, port0 in external bus mode, ale, psen i oh = ? 3.2 ma v dd ? 0.7 - - v i il low-level input current v i = 0.4 v, ports 1, 2, 3, 4 ? 1- ? 75 ? a
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 72 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi [1] this parameter is measured only for initial qualification and af ter a design or process change that could affect this parameter. [2] under steady state (non-transient) conditions, i ol must be externally limited as follows: a) maximum i ol per 8-bit port: 26 ma b) maximum i ol total for all outputs: 71 ma c) if i ol exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. [3] capacitive loading on ports 0 and 2 may caus e spurious noise to be superimposed on the v ol of ale and ports 1 and 3. the noise due to external bus capacitance discharging into the port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the al e pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an addr ess latch with a schmitt trigger strobe input. [4] load capacitance for port 0, ale and psen = 100 pf, load capacitance for all other outputs = 80 pf. [5] capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v dd ? 0.7 specification when the address bits are stabilizing. [6] pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curre nt reaches its maximum value when v i is approximately 2 v. [7] pin capacitance is characterized but not tested. ea = 25 pf (max). i thl high-low transition current v i = 2 v, ports 1, 2, 3, 4 [6] -- ? 650 ? a i li input leakage current 0.45 v < v i p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 73 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi (1) maximum active i dd (2) maximum idle i dd (3) typical active i dd (4) typical idle i dd fig 35. i dd vs. frequency internal clock frequency (mhz) 0 40 30 20 10 002aaa813 20 30 10 40 50 i dd (ma) 0 (1) (2) (3) (4)
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 74 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 9. dynamic characteristics [1] t cy(clk) = 1 / f osc . [2] calculated values ar e for 6-clock mode only. table 71. dynamic characteristics over operating conditions: load capacitance for port 0, ale, and psen = 100 pf; load capacitance for all other outputs = 80 pf t amb = ? 40 ? cto+85 ? c; v dd = 4.5 v to 5.5 v; v ss =0v [1] [2] symbol parameter conditions min typ max unit f osc oscillator frequency 12-clock mode 0 - 40 mhz 6-clock mode 0 - 20 mhz iap 0.25 - 40 mhz t lhll ale pulse width 2t cy(clk) ? 15 - - ns t avll address valid to ale low time t cy(clk) ? 15 - - ns t llax address hold after ale low time t cy(clk) ? 15 - - ns t lliv ale low to valid instruction in time - - 4t cy(clk) ? 45 ns t llpl ale low to psen low time t cy(clk) ? 15 - - ns t plph psen pulse width 3t cy(clk) ? 15 - - ns t pliv psen low to valid instruction in time --3t cy(clk) ? 50 ns t pxix input instruction hold after psen time 0 - - ns t pxiz input instruction float after psen time - - t cy(clk) ? 15 ns t pxav psen to address valid time t cy(clk) ? 8- - ns t aviv address to valid instruction in time - - 5t cy(clk) ? 60 ns t plaz psen low to address float time - - 10 ns t rlrh rd low pulse width 6t cy(clk) ? 30 - - ns t wlwh wr low pulse width 6t cy(clk) ? 30 - - ns t rldv rd low to valid data in time - - 5t cy(clk) ? 50 ns t rhdx data hold after rd time 0 - - ns t rhdz data float after rd time - - 2t cy(clk) ? 12 ns t lldv ale low to valid data in time - - 8t cy(clk) ? 50 ns t avdv address to valid data in time - - 9t cy(clk) ? 75 ns t llwl ale low to rd or wr low time 3t cy(clk) ? 15 - 3t cy(clk) + 15 ns t avwl address to rd or wr low time 4t cy(clk) ? 30 - - ns t whqx data hold after wr time t cy(clk) ? 20 - - ns t qvwh data output valid to wr high time 7t cy(clk) ? 50 - - ns t rlaz rd low to address float time - - 0 ns t whlh rd or wr high to ale high time t cy(clk) ? 15 - t cy(clk) + 15 ns
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 75 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 9.1 explanation of symbols each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their posit ions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a ? address c ? clock d ? input data h ? logic level high i ? instruction (program memory contents) l ? logic level low or ale p ? psen q ? output data r ? rd signal t ? time v ? valid w ? wr signal x ? no longer a valid logic level z ? high impedance (float) example: t avll = address valid to ale low time t llpl = ale low to psen low time fig 36. external program memory read cycle 002aaa548 port 2 psen ale a0 to a7 t llax t plaz t pxiz t llpl t aviv t avll t lliv t pliv t plph instr in a8 to a15 a8 to a15 a0 to a7 port 0 t pxix t pxav t lhll
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 76 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 37. external data memory read cycle ale psen port 0 port 2 rd a0 to a7 from ri to dpl data in a0 to a7 from pcl instr in p2.0 to p2.7 or a8 to a15 from dph a0 to a15 from pch t lldv 002aaa549 t whlh t avdv t llwl t avll t avwl t rlrh t rldv t llax t rhdz t rhdx t rlaz fig 38. external data memory write cycle 002aaa550 port 2 port 0 wr psen ale t lhll p2[7:0] or a8 to a15 from dph a0 to a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t whqx t whlh a8 to a15 from pch a0 to a7 from pcl
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 77 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi table 72. external clock drive symbol parameter oscillator unit 40 mhz variable min max min max f osc oscillator frequency - - 0 40 mhz t cy(clk) clock cycle time 25 - - - ns t chcx clock high time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clcx clock low time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clch clock rise time - 10 - - ns t chcl clock fall time - 10 - - ns fig 39. external clock drive waveform t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 73. serial port timing symbol parameter oscillator unit 40 mhz variable min max min max t xlxl serial port clock cycle time 0.3 - 12t cy(clk) - ? s t qvxh output data set-up to clock rising edge time 117 - 10t cy(clk) ?? 133 - ns t xhqx output data hold after clock rising edge time 0- 2t cy(clk) ?? 50 - ns t xhdx input data hold after clock rising edge time 0- 0 - ns t xhdv input data valid to clock rising edge time - 117 - 10t cy(clk) ?? 133 ns
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 78 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi [1] at 100 kb/s. all other bit rates, this value is inversely proportional to the bit rate of 100 kb/s. [2] determined by the external bus capacitanc e and pull-up resistor. this must be < 1 ? s. [3] spikes on sda and scl with a duration less than 3t cy(clk) will be filtered out. max capacitance on sda and scl = 400 pf. fig 40. shift register mode timing waveforms 002aaa552 ale 0 instruction 1 2 3 4 5 6 7 8 0 1234567 valid valid valid valid valid valid valid valid t xlxl set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri table 74. i 2 c-bus interface timing (12-clock mode) symbol parameter conditions input output unit t hd;sta hold time (repeated) start condition ? 14t cy(clk) > 4.0 [1] ? s t low low period of the scl clock ? 16t cy(clk) > 4.7 [1] ? s t high high period of the uscl clock ? 14t cy(clk) > 4.0 [1] ? s t r(scl) scl rise time ? 1- [2] ? s t f(scl) scl fall time ? 0.3 ? 0.3 [3] ? s t su;dat data set-up time ? 250 20t cy(clk) ? t r(sda) ns t sudat1 data set-up time 1 before repeated start ? 250 > 1000 [1] ns t sudat2 data set-up time 2 before stop condition ? 250 > 8t cy(clk) ns t hd;dat data hold time ? 0> 8t cy(clk) ? t f(scl) ns t su;sta set-up time for a repeated start condition ? 14t cy(clk) [1] > 4.7 [1] ? s t su;sto set-up time for stop condition ? 14t cy(clk) [1] > 4.0 [1] ? s t buf bus free time between a stop and start condition ? 14t cy(clk) [1] > 4.7 [1] ? s t r(sda) sda rise time ? 0.3 ? 0.3 ? s t f(sda) sda fall time ? 0.3 ? 0.3 [3] ? s
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 79 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 41. i 2 c-bus interface timing 002aab861 t hd;sta t rcl t rda t su;sta t low t high t su;dat t hd;dat t sudat1 scl (input/ output) sda (input/ output) start or repeated start condition t fcl 0.7v cc 0.3v cc t sudat2 t su;sto repeated start condition stop condition start condition 0.7v cc 0.3v cc t fda t buf table 75. spi interface timing symbol parameter conditions variable clock f osc =18mhz unit min max min max f spi spi operating frequency 0 t cy(clk) /4 0 10 mhz t spicyc spi cycle time see figure 42 , 43 , 44 , 45 4t cy(clk) - 222 - ns t spilead spi enable lead time see figure 44 , 45 250 - 250 - ns t spilag spi enable lag time see figure 44 , 45 250 - 250 - ns t spiclkh spiclk high time see figure 42 , 43 , 44 , 45 2t cy(clk) -1 1 1-n s t spiclkl spiclk low time see figure 42 , 43 , 44 , 45 2t cy(clk) -1 1 1-n s t spidsu spi data set-up time master or slave; see figure 42 , 43 , 44 , 45 100 - 100 - ns t spidh spi data hold time master or slave; see figure 42 , 43 , 44 , 45 100 - 100 - ns t spia spi access time see figure 44 , 45 0 80 0 80 ns t spidis spi disable time see figure 44 , 45 0 160 - 160 ns t spidv spi enable to output data valid time see figure 42 , 43 , 44 , 45 -1 1 1-1 1 1n s t spioh spi output data hold time see figure 42 , 43 , 44 , 45 0-0-n s t spir spi rise time see figure 42 , 43 , 44 , 45 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 42 , 43 , 44 , 45 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 80 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 42. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 43. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 81 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 44. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spif t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined fig 45. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidh t spidh t spif t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input)
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 82 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 46. test load example all other pins disconnected fig 47. i dd test condition, active mode all other pins disconnected fig 48. i dd test condition, idle mode 002aaa555 to dut to tester c l 002aaa556 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd v dd 8 dut 002aaa557 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd 8 dut
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 83 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi all other pins disconnected fig 49. i dd test condition, power-down mode 002aaa558 v dd v dd = 2 v v dd p0 ea rst xtal2 (n.c.) xtal1 v ss i dd v dd 8 dut
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 84 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 10. package outline fig 50. package outline sot376-1 (tqfp44) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.45 0.30 0.18 0.12 10.1 9.9 0.8 12.15 11.85 1.2 0.8 7 0 o o 0.2 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot376-1 137e08 ms-026 00-01-19 02-03-14 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.2 0.8 d b p e e b 11 d h b p e h v m b d z d a z e e v m a 1 44 34 33 23 22 12 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale tqfp44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm sot376-1 pin 1 index
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 85 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi fig 51. package outline sot187-2 (plcc44) unit a a 1 min. a 4 max. b p ey wv references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 86 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 11. abbreviations table 76. acronym list acronym description ale address latch enabled cpu central processing unit dut device under test eprom erasable programmable read-only memory emi electro-magnetic interference mcu microcontroller unit pwm pulse width modulator ram random access memory rc resistance-capacitance sfr special function register spi serial peripheral interface uart universal asynchronous receiver/transmitter
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 87 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 12. revision history table 77. revision history document id release date data sheet status change notice supersedes p89v660_662_664 v.3.1 20111017 product data sheet - p89v660_662_664 v.3 modifications: ? table 3 ? pin description ? : added table note 1 . ? updated equation 2 and equation 3 . ? removed type numbers p89v660fa and p89v660fbc from table 1 and ta b l e 2 due to eol. p89v660_662_664 v.3 20081110 product data sheet - p89v660_662_664 v.2 modifications: ? section 2.2 ? additional features ? : corrected 6-clock/12-cl ock mode information. p89v660_662_664 v.2 20080129 product data sheet - p89v660_662_664 v.1 p89v660_662_664 v.1 20070502 product data sheet - -
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 88 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 13.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 13.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
p89v660_662_664 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3.1 ? 17 october 2011 89 of 90 nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 13.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 14. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors p89v660/662/664 80c51 with 512 b/1 kb/2 kb ram, dual i 2 c-bus, spi ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 october 2011 document identifier: p89v660_662_664 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 1 2.3 comparison to the p89c660/662/664 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . 10 6.1 special function registers . . . . . . . . . . . . . . . . 10 6.2 memory organization . . . . . . . . . . . . . . . . . . . 14 6.2.1 expanded data ram addressing . . . . . . . . . . 14 6.2.2 dual data pointers. . . . . . . . . . . . . . . . . . . . . . 16 6.2.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 flash organization . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 boot block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 power-on reset code execution . . . . . . . . . . . 19 6.3.5 hardware activation of the bootloader . . . . . . 19 6.3.6 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.7 using isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.8 iap method. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 i 2 c-bus interface. . . . . . . . . . . . . . . . . . . . . . . 24 6.4.1 i 2 c-bus data register. . . . . . . . . . . . . . . . . . . . 26 6.4.2 i 2 c-bus slave address register . . . . . . . . . . . . 26 6.4.3 i 2 c-bus control register. . . . . . . . . . . . . . . . . . 26 6.4.4 i 2 c-bus status register . . . . . . . . . . . . . . . . . . 28 6.4.5 i 2 c-bus operation modes . . . . . . . . . . . . . . . . 28 6.4.5.1 master transmitter mode. . . . . . . . . . . . . . . . . 28 6.4.5.2 master receiver mode . . . . . . . . . . . . . . . . . . . 29 6.4.5.3 slave receiver mode . . . . . . . . . . . . . . . . . . . . 30 6.4.5.4 slave transmitter mode. . . . . . . . . . . . . . . . . . 30 6.5 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 38 6.5.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.5.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.6 timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.6.1 capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.2 auto-reload mode (up or down-counter). . . . . 45 6.6.3 programmable clock-out. . . . . . . . . . . . . . . . . 46 6.6.4 baud rate generator mode . . . . . . . . . . . . . . . 47 6.6.5 summary of baud rate equations. . . . . . . . . . 48 6.7 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.7.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.7.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.7.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.7.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.7.5 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.7.6 more about uart mode 1 . . . . . . . . . . . . . . . 50 6.7.7 more about uart modes 2 and 3 . . . . . . . . . 50 6.7.8 multiproce ssor communications. . . . . . . . . . . 51 6.7.9 automatic address recognition. . . . . . . . . . . . 51 6.8 serial peripheral interfac e (spi) . . . . . . . . . . 53 6.8.1 spi features . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.8.2 spi description. . . . . . . . . . . . . . . . . . . . . . . . 53 6.9 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 56 6.10 pca . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.10.1 pca capture mode. . . . . . . . . . . . . . . . . . . . . 60 6.10.2 16-bit software timer mode . . . . . . . . . . . . . . 61 6.10.3 high-speed output mode . . . . . . . . . . . . . . . . 62 6.10.4 pulse width modulator mode . . . . . . . . . . . . . 63 6.10.5 pca watchdog timer . . . . . . . . . . . . . . . . . . . 64 6.11 security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.12 interrupt priority and polling sequence. . . . . . 65 6.13 power-saving modes . . . . . . . . . . . . . . . . . . . 68 6.13.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.13.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 69 6.14 system clock and clock options . . . . . . . . . . . 70 6.14.1 clock input options and recommended capacitor values for the oscillator. . . . . . . . . . 70 6.14.2 clock doubling option. . . . . . . . . . . . . . . . . . . 70 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 71 8 static characteristics . . . . . . . . . . . . . . . . . . . 71 9 dynamic characteristics. . . . . . . . . . . . . . . . . 74 9.1 explanation of symbols . . . . . . . . . . . . . . . . . 75 10 package outline. . . . . . . . . . . . . . . . . . . . . . . . 84 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 86 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 87 13 legal information . . . . . . . . . . . . . . . . . . . . . . 88 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 88 13.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14 contact information . . . . . . . . . . . . . . . . . . . . 89 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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